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公开(公告)号：US11748202B2
公开(公告)日：2023-09-05
申请号：US17901337
申请日：2022-09-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Devanathan Varadarajan , Ramakrishnan Venkatasubramanian , Varun Singh
CPC classification number: G06F11/1448 , H03M7/30 , G06F2201/82
Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.
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公开(公告)号：US11568951B2
公开(公告)日：2023-01-31
申请号：US16817096
申请日：2020-03-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Francisco Adolfo Cano , Devanathan Varadarajan , Anthony Martin Hill
IPC: G11C29/00 , G11C29/38 , G11C29/50 , G11C11/419 , G11C11/418 , G11C11/412
Abstract: Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.
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公开(公告)号：US11436090B2
公开(公告)日：2022-09-06
申请号：US17125244
申请日：2020-12-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Devanathan Varadarajan , Ramakrishnan Venkatasubramanian , Varun Singh
Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.
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公开(公告)号：US09053799B2
公开(公告)日：2015-06-09
申请号：US14038306
申请日：2013-09-26
Applicant: Texas Instruments Incorporated
Inventor： Devanathan Varadarajan , Harsharaj Ellur
CPC classification number: G11C29/4401 , G11C17/16 , G11C17/18 , G11C29/38 , G11C29/785 , G11C29/789 , G11C2029/4402
Abstract: A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each memory wrapper includes a memory block with a fuse register and a bypass register. The bypass register has a bypass data that indicates a defective memory wrapper of the plurality of memory wrappers. A fuseROM controller is coupled to the plurality of memory wrappers. A memory bypass chain links the bypass registers in the plurality of memory wrappers with the fuseROM controller. The fuseROM controller loads the bypass data in the memory bypass chain. A memory data chain links the fuse registers in the plurality of memory wrappers with the fuseROM controller. The memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain.
Abstract translation: 集成电路（IC）中的存储器修复系统，其优化用于存储器修复的熔丝ROM。 IC包括多个存储器包装器。 每个存储器包装器包括具有熔丝寄存器和旁路寄存器的存储器块。 旁路寄存器具有指示多个存储器包装器的有缺陷的存储器包装器的旁路数据。 熔丝ROM控制器耦合到多个存储器包装器。 存储器旁路链将多个存储器封装器中的旁路寄存器与熔丝ROM控制器链接。 fuseROM控制器将旁路数据加载到内存旁路链中。 存储器数据链将多个存储器包装器中的熔丝寄存器与熔丝ROM控制器链接。 存储器数据链被重新配置为响应于加载在存储器旁路链中的旁路数据，将多个存储器包装器中的一组缺陷存储器包装器中的熔丝寄存器链接。
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公开(公告)号：US12259789B2
公开(公告)日：2025-03-25
申请号：US18239880
申请日：2023-08-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Devanathan Varadarajan , Ramakrishnan Venkatasubramanian , Varun Singh
Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.
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Patent Agency Ranking
公开(公告)号：US12085610B2
公开(公告)日：2024-09-10
申请号：US17877607
申请日：2022-07-29
Applicant: Texas Instruments Incorporated
Inventor： Devanathan Varadarajan , Benjamin Niewenhuis
IPC: G01R31/317 , G01R31/3177 , G01R31/28 , G01R31/3185
CPC classification number: G01R31/31703 , G01R31/3177 , G01R31/2851 , G01R31/31724 , G01R31/318536 , G01R31/318547 , G01R31/318566 , G01R31/318586
Abstract: An example device includes built in test observation controller circuitry configured to: obtain a test; send first instructions to the processor to begin to execute the test by modifying values stored in a plurality of memory circuits; send second instructions to the processor to stop execution of the test at a first simulation time, wherein one or more memory values that are unobservable during a second simulation time of the test execution are observable during the first simulation time; and enhanced chip access trace scan circuitry configured to select a subset of the values from the plurality of memory circuits while the test is stopped; and signature circuitry configured to: determine a logic signature based on the subset of the values; and provide the logic signature for comparison to an expected signature, wherein a difference between the logic signature and the expected signature corresponds to a fault in the processor.
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公开(公告)号：US12033711B2
公开(公告)日：2024-07-09
申请号：US18301327
申请日：2023-04-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Devanathan Varadarajan , Varun Singh
CPC classification number: G11C29/4401 , G11C29/16 , G11C29/40
Abstract: In a described example, an integrated circuit (IC) includes a repairable memory system. A repair controller is coupled to the repairable memory system. The repair controller includes compression logic configured to encode memory repair code data for a respective instance of the repairable memory system and provide compressed repair data. A non-volatile memory controller is coupled to the repair controller and to non-volatile memory. The non-volatile memory controller is configured to transfer the compressed repair data to the non-volatile memory for storage.
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公开(公告)号：US11881275B2
公开(公告)日：2024-01-23
申请号：US18148312
申请日：2022-12-29
Applicant: Texas Instruments Incorporated
Inventor： Francisco Adolfo Cano , Devanathan Varadarajan , Anthony Martin Hill
IPC: G11C29/00 , G11C29/38 , G11C29/50 , G11C11/419 , G11C11/418 , G11C11/412
CPC classification number: G11C29/38 , G11C11/412 , G11C11/418 , G11C11/419 , G11C29/50004 , G11C2029/5004
Abstract: Systems of screening memory cells of a memory include modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven with respect to a nominal operating voltage on the wordline. In a write operation, one or both of the bitline and wordline may be overdriven or underdriven with respect to corresponding a nominal operating voltage. Such a system has margin control circuity, which may be in the form of bitline and wordline margin controls, to modulate bitline and wordline voltages, respectively, in the memory cells of the memory array.
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公开(公告)号：US11631472B2
公开(公告)日：2023-04-18
申请号：US17125323
申请日：2020-12-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Devanathan Varadarajan , Varun Singh
Abstract: In a described example, an integrated circuit (IC) includes a repairable memory system. A repair controller is coupled to the repairable memory system. The repair controller includes compression logic configured to encode memory repair code data for a respective instance of the repairable memory system and provide compressed repair data. A non-volatile memory controller is coupled to the repair controller and to non-volatile memory. The non-volatile memory controller is configured to transfer the compressed repair data to the non-volatile memory for storage.
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公开(公告)号：US20220413966A1
公开(公告)日：2022-12-29
申请号：US17901337
申请日：2022-09-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Devanathan Varadarajan , Ramakrishnan Venkatasubramanian , Varun Singh
Abstract: One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.
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