公开(公告)号：US10250248B2

公开(公告)日：2019-04-02

申请号：US16057979

申请日：2018-08-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srikanth Manian ,  Srinivas Theertham ,  Jagdish Chand ,  Dinesh Jain

IPC: H03M1/66 ,  H03K5/26 ,  H03L7/18 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03K5/15 ,  H03K5/135

Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

公开(公告)号：US20180351541A1

公开(公告)日：2018-12-06

申请号：US16057979

申请日：2018-08-08

Applicant: Texas Instruments Incorporated

Inventor： Srikanth Manian ,  Srinivas Theertham ,  Jagdish Chand ,  Dinesh Jain

IPC: H03K5/26 ,  H03L7/18 ,  H03L7/07 ,  H03L7/08 ,  H03K5/15 ,  H03K5/135 ,  H03L7/081

CPC classification number: H03K5/26 ,  H03K5/135 ,  H03K5/1502 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/18

Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

公开(公告)号：US10075156B2

公开(公告)日：2018-09-11

申请号：US15673166

申请日：2017-08-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srikanth Manian ,  Srinivas Theertham ,  Jagdish Chand ,  Dinesh Jain

IPC: H03M1/66 ,  H03K5/26 ,  H03K5/135 ,  H03L7/081 ,  H03L7/08 ,  H03L7/07 ,  H03L7/18 ,  H03K5/15

CPC classification number: H03K5/26 ,  H03K5/135 ,  H03K5/1502 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/18

Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

公开(公告)号：US09705507B1

公开(公告)日：2017-07-11

申请号：US15158622

申请日：2016-05-19

Applicant: Texas Instruments Incorporated

Inventor： Dinesh Jain

IPC: H03K21/00 ,  H03K21/02 ,  H03K5/05 ,  H03K23/58

CPC classification number: H03K21/026 ,  H03K5/05 ,  H03K23/58

Abstract: Disclosed examples include frequency divider circuits to divide a high frequency first clock signal to generate an output clock signal at a lower frequency, including a delay circuit to provide a delayed clock signal, a divider circuit to provide a divided clock signal, a sub-sampling circuit to sub-sample the first clock signal with the divided clock signal, and a feedback circuit to set the delay value of the adjustable delay circuit according to the sub-sampled output signal.

公开(公告)号：US20170111053A1

公开(公告)日：2017-04-20

申请号：US15235477

申请日：2016-08-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dinesh Jain

IPC: H03M1/10 ,  H03M1/12 ,  H03M1/34

CPC classification number: H03M1/1009 ,  H03M1/12 ,  H03M1/1245 ,  H03M1/34 ,  H03M1/56

Abstract: An analog to digital converter includes an analog input and a voltage comparator coupled to the analog input for comparing a voltage at the analog input to a digitally synthesized waveform. A digital to analog converter (DAC) generates the digitally synthesized waveform. The DAC includes a plurality of capacitors selectively connected in parallel wherein the period between the selection of capacitors is less than the settling time of the voltage across the capacitors.