公开(公告)号：US20240213333A1

公开(公告)日：2024-06-27

申请号：US18145625

申请日：2022-12-22

Applicant: Texas Instruments Incorporated

Inventor： Fuchao Wang ,  Bill Wofford ,  Jonathan R Garrett ,  Ebenezer Eshun ,  Jungwoo Joh

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/3105 ,  H01L23/495 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/408 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31053 ,  H01L23/4952 ,  H01L23/49562 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

Abstract: A microelectronic device includes a III-N semiconductor layer having a top surface with at least one topological structure in the III-N semiconductor layer. The topological structure may be an opening in the III-N semiconductor layer or a protrusion of the III-N semiconductor layer. The microelectronic device also includes a liner including silicon nitride on the topological structure, contacting the III-N semiconductor layer. The microelectronic device further includes a fill material including silicon nitride on the topological structure on the liner. A top surface of the fill material is planar and parallel to the top surface of the III-N semiconductor layer adjacent to the topological structure.

公开(公告)号：US09406769B2

公开(公告)日：2016-08-02

申请号：US14875343

申请日：2015-10-05

Applicant: Texas Instruments Incorporated

Inventor： Shashank S. Ekbote ,  Kwan-Yong Lim ,  Ebenezer Eshun ,  Youn Sung Choi

IPC: H01L29/08 ,  H01L29/45 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/161 ,  H01L21/28 ,  H01L29/78 ,  H01L29/165 ,  H01L29/417

CPC classification number: H01L29/45 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

公开(公告)号：US09224653B2

公开(公告)日：2015-12-29

申请号：US14726691

申请日：2015-06-01

Applicant: Texas Instruments Incorporated

Inventor： Himadri Sekhar Pal ,  Ebenezer Eshun ,  Shashank S. Ekbote

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/11 ,  H01L21/311 ,  H01L21/265

CPC classification number: H01L21/823425 ,  H01L21/26513 ,  H01L21/311 ,  H01L21/823412 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/1104 ,  H01L27/1116 ,  H01L28/20 ,  H01L29/66477

Abstract: In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional masking steps.

公开(公告)号：US09093298B2

公开(公告)日：2015-07-28

申请号：US13972973

申请日：2013-08-22

Applicant: Texas Instruments Incorporated

Inventor： Shashank S. Ekbote ,  Kwan-Yong Lim ,  Ebenezer Eshun ,  Youn Sung Choi

IPC: H01L21/336 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/45 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

公开(公告)号：US09076670B2

公开(公告)日：2015-07-07

申请号：US13943786

申请日：2013-07-16

Applicant: Texas Instruments Incorporated

Inventor： Himadri Sekhar Pal ,  Ebenezer Eshun ,  Shashank S. Ekbote

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823425 ,  H01L21/26513 ,  H01L21/311 ,  H01L21/823412 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/1104 ,  H01L27/1116 ,  H01L28/20 ,  H01L29/66477

Abstract: In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional masking steps.

Abstract translation: 在包括NMOS逻辑晶体管，NMOS SRAM晶体管和电阻器的集成电路中，在掺杂电阻器的同时掺杂SRAM晶体管的栅极，从而允许逻辑晶体管的栅极被单独掺杂 而不需要任何额外的掩蔽步骤。

公开(公告)号：US20150021706A1

公开(公告)日：2015-01-22

申请号：US13943786

申请日：2013-07-16

Applicant: Texas Instruments Incorporated

Inventor： Himadri Sekhar Pal ,  Ebenezer Eshun ,  Shashank S. Ekbote

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823425 ,  H01L21/26513 ,  H01L21/311 ,  H01L21/823412 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/1104 ,  H01L27/1116 ,  H01L28/20 ,  H01L29/66477

Abstract: In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional masking steps.

公开(公告)号：US20130093024A1

公开(公告)日：2013-04-18

申请号：US13654015

申请日：2012-10-17

Applicant: Texas Instruments Incorporated

Inventor： Ebenezer Eshun

IPC: H01L21/02 ,  H01L27/06

CPC classification number: H01L29/8605 ,  H01L27/0629 ,  H01L28/20

Abstract: An integrated circuit having a replacement HiK metal gate transistor and a front end SiCr resistor. The SiCr resistor replaces the conventional polysilicon resistor in front end processing and is integrated into the contact module. The first level of metal interconnect is located above the SiCr resistor. First contacts connect to source/drain regions. Second contacts electrically connect the first level of interconnect to either the SiCr resistor or the metal replacement gate.

Abstract translation: 具有替代的HiK金属栅极晶体管和前端SiCr电阻器的集成电路。 SiCr电阻器替代了前端处理中的常规多晶硅电阻器，并集成到触点模块中。 第一级金属互连位于SiCr电阻上方。 第一个触点连接到源/漏区。 第二触点将第一级互连电连接到SiCr电阻器或金属替代栅极。