公开(公告)号：US20220068649A1

公开(公告)日：2022-03-03

申请号：US17411431

申请日：2021-08-25

Applicant: Texas Instruments Incorporated

Inventor： Mona M. Eissa ,  Jason R. Heine ,  Pushpa Mahalingam ,  Henry Litzmann Edwards ,  James Robert Todd ,  Alexei Sadovnikov

IPC: H01L21/266 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

Abstract: A method of fabricating an IC includes providing a substrate including a semiconductor surface having well diffusions for a plurality of devices including bipolar, complementary metal oxide semiconductor (CMOS), and double-diffused MOS (DMOS) devices. A polysilicon layer is deposited on a dielectric layer over the semiconductor surface, an anti-reflective coating (ARC) layer is formed on the polysilicon layer, and a photoresist pattern is formed on the ARC layer. The ARC layer is etched in areas exposed by the photoresist pattern to define areas including gate areas having the ARC layer on the polysilicon layer. The photoresist pattern is removed. Polysilicon etching is performed in areas lacking the ARC layer to form polysilicon gates having a remaining ARC portion of the ARC layer thereon. A self-aligned ion implant uses the remaining ARC portion as an additional implant blocking layer for the polysilicon gates, and the remaining ARC portion is stripped.

公开(公告)号：US11152505B2

公开(公告)日：2021-10-19

申请号：US16021601

申请日：2018-06-28

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Andrew Derek Strachan ,  Henry Litzmann Edwards ,  Dhanoop Varghese ,  Xiaoju Wu ,  Binghua Hu ,  James Robert Todd

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265 ,  H01L29/08 ,  H01L21/266

Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.

公开(公告)号：US10903356B2

公开(公告)日：2021-01-26

申请号：US15865028

申请日：2018-01-08

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Binghua Hu ,  James Robert Todd

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167 ,  H01L21/265 ,  H01L21/324 ,  H01L29/423

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate having a p-epi layer thereon, a p-body region in the p-epi layer and an ndrift (NDRIFT) region within the p-body to provide a drain extension region. A gate stack includes a gate dielectric layer over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region. A patterned gate electrode is on the gate dielectric. A DWELL region is within the p-body region. A source region is within the DWELL region, and a drain region is within the NDRIFT region. An effective channel length (Leff) for the LDMOS device is 75 nm to 150 nm which evidences a DWELL implant that utilized an edge of the gate electrode to delineate an edge of a DWELL ion implant so that the DWELL region is self-aligned to the gate electrode.

公开(公告)号：US10748818B2

公开(公告)日：2020-08-18

申请号：US16231243

申请日：2018-12-21

Applicant: Texas Instruments Incorporated

Inventor： Tathagata Chatterjee ,  Steven Loveless ,  James Robert Todd ,  Andrew Strachan

IPC: H01L49/02 ,  H01L21/8234 ,  H01L21/762 ,  H01L23/528 ,  H01L23/00 ,  H01L23/532

Abstract: In various examples, a method and apparatus are provided to achieve dynamic biasing to mitigate electrical stress. Described examples include a device includes a first resistor portion having a first terminal and a second terminal, and a second resistor portion having a third terminal and a fourth terminal. The device also includes a well in a substrate proximate to the first resistor portion and the second resistor portion and an insulating layer between the well and the first resistor portion and the second resistor portion. The device also includes a transistor having a control terminal coupled to the second terminal of the first resistor portion and the third terminal of the second resistor portion, the transistor having a first current-handling terminal coupled to a first voltage and a second current-handling terminal coupled to a current source and to the well.

公开(公告)号：US10096685B2

公开(公告)日：2018-10-09

申请号：US15406913

申请日：2017-01-16

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  Binghua Hu ,  James Robert Todd

IPC: H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L29/167 ,  H01L21/324 ,  H01L21/265 ,  H01L21/762 ,  H01L21/225 ,  H01L29/78 ,  H01L29/66 ,  H01L21/266

Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.

公开(公告)号：US20240230721A1

公开(公告)日：2024-07-11

申请号：US18404873

申请日：2024-01-04

Applicant: Texas Instruments Incorporated

Inventor： Rushil Kishore Kumar ,  James Robert Todd ,  Jasjot Singh Chadha ,  Anand Kannan ,  Naresh Lagadapati ,  Rejin K. Raveendranath

IPC: G01R15/14 ,  G01R19/00

CPC classification number: G01R15/146 ,  G01R19/0046

Abstract: A semiconductor device includes a resistor head, a resistor body, and a sense terminal. The resistor head is constructed using a first material. The resistor body is coupled to the resistor head and is constructed using a second material having a higher resistivity than the first material. The sense terminal has a first section and a second section and is decoupled from the resistor head, in which the second section of the sense terminal is coupled between the first section of the sense terminal and the resistor body, with an end portion of the second section of the sense terminal coupled to the resistor body.

公开(公告)号：US11581309B2

公开(公告)日：2023-02-14

申请号：US17675066

申请日：2022-02-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Szelong ,  James Robert Todd ,  Tobias Bernhard Fritz ,  Ralf Peter Brederlow

IPC: H01L27/08 ,  G01L1/18 ,  H01L49/02

Abstract: An integrated circuit comprises a semiconductor substrate having a surface. A lateral resistor is arranged in a first plane parallel to the surface of the substrate. A vertical reference resistor comprises a layer arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. This layer is doped to promote current flow in the second plane. The vertical reference resistor further comprises a first trench and a second trench coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and the second planes and are doped to impede current flow in the vertical direction. A cross-section of the first and second trenches is two-fold rotationally symmetric around the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.

公开(公告)号：US10861948B2

公开(公告)日：2020-12-08

申请号：US16683517

申请日：2019-11-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Binghua Hu ,  James Robert Todd

IPC: H01L29/40 ,  H01L29/78 ,  H01L21/32 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/266 ,  H01L27/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/265 ,  H01L21/324 ,  H01L21/762 ,  H01L29/06 ,  H01L29/167 ,  H01L21/225

Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.

公开(公告)号：US20200083336A1

公开(公告)日：2020-03-12

申请号：US16683517

申请日：2019-11-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann Edwards ,  Binghua Hu ,  James Robert Todd

IPC: H01L29/40 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/167 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/324 ,  H01L21/32 ,  H01L21/265 ,  H01L21/266 ,  H01L21/225

Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.

公开(公告)号：US10461182B1

公开(公告)日：2019-10-29

申请号：US16021772

申请日：2018-06-28

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards ,  James Robert Todd ,  Binghua Hu ,  Xiaoju Wu ,  Stephanie L. Hilbun

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10

Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.