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公开(公告)号:US11257814B2
公开(公告)日:2022-02-22
申请号:US16428682
申请日:2019-05-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Michael Szelong , James Robert Todd , Tobias Bernhard Fritz , Ralf Peter Brederlow
Abstract: An integrated circuit comprises a semiconductor substrate having a surface. A lateral resistor is arranged in a first plane parallel to the surface of the substrate. A vertical reference resistor comprises a layer arranged in a second plane parallel to the surface of the substrate and deeper than the first plane. This layer is doped to promote current flow in the second plane. The vertical reference resistor further comprises a first trench and a second trench coupled between the layer and the surface of the substrate. The first and second trenches are arranged in a vertical direction orthogonal to the first and the second planes and are doped to impede current flow in the vertical direction. A cross-section of the first and second trenches is two-fold rotationally symmetric around the vertical direction, and the lateral resistor and the first and second trenches have the same temperature coefficient.
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公开(公告)号:US20220020915A1
公开(公告)日:2022-01-20
申请号:US16932343
申请日:2020-07-17
Applicant: Texas Instruments Incorporated
Inventor: Umidjon Nurmetov , Ralf Peter Brederlow , Baher Haroun , Jose Antonio Vieira Formenti , Michael Szelong , Tobias Bernhard Fritz
IPC: H01L41/113 , H01L41/04 , G01L1/22 , G01L1/18
Abstract: In described examples, a circuit includes an analog frontend arranged to generate an analog stress compensating signal in response to a to-be-compensated analog signal and a first-axis stress sensing signal. The analog frontend can comprise a first precision component (e.g., 220) arranged on a piezoelectric material and arranged to generate the to-be-compensated analog signal that is affected by a stress exerted in the piezoelectric material and a directional stress sensor arranged on the piezoelectric material and coupled to the first precision component. The directional stress sensor is arranged to generate the first-axis sensing signal in response to a longitudinal resultant of a stress exerted in the piezoelectric material. A compensating circuit is arranged to generate a compensated output signal in response to the compensating analog signal and to-be-compensated analog signal.
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公开(公告)号:US10320589B1
公开(公告)日:2019-06-11
申请号:US15859419
申请日:2017-12-30
Applicant: Texas Instruments Incorporated
Inventor: Swaminathan Sankaran , Bradley Allen Kramer , Baher Haroun , Tobias Bernhard Fritz , Ernst Georg Muellner , Ralf Peter Brederlow
IPC: H04L25/02 , H05K1/02 , H04B3/54 , G01R31/317 , H04B1/525 , H03K17/693
CPC classification number: H04L25/0276 , G01R31/31706 , H03K17/693 , H04B1/525 , H04B3/542 , H05K1/0233
Abstract: Described examples include an integrated circuit including a receive portion to receive an encoded transmission on a line. The receive portion has: a wake mode in which the receiver is capable of receiving the encoded transmission; and a sleep mode in which the receiver is not capable of receiving the encoded transmission. A wakeup controller monitors the line for a wakeup signal and provides a signal to the receive portion to cause the receive portion to enter the wake mode when the wakeup controller receives the wakeup signal.
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公开(公告)号:US20250017113A1
公开(公告)日:2025-01-09
申请号:US18886687
申请日:2024-09-16
Applicant: Texas Instruments Incorporated
Inventor: Umidjon Nurmetov , Ralf Peter Brederlow , Baher Haroun , Jose Antonio Vieira Formenti , Michael Szelong , Tobias Bernhard Fritz
Abstract: In described examples, a circuit includes a substrate and a first resistor on the substrate, the first resistor in a first direction. The circuit also includes a second resistor on the substrate, the second resistor coupled to the first resistor, the second resistor in a second direction, the second direction and the first direction transversely oriented and a device on the substrate.
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公开(公告)号:US10547268B2
公开(公告)日:2020-01-28
申请号:US15858485
申请日:2017-12-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Tobias Bernhard Fritz , Martin Staebler , Baher Haroun , Peter Fundaro , Jiri Panacek , Ralf Peter Brederlow
Abstract: A motor drive circuit includes a first serializer-deserializer (SER-DES) module that converts first SER-DES input signals into a first SER-DES output serial data stream. The first SER-DES input signals relate to motor control inputs or motor drive power outputs. A second SER-DES module converts a second SER-DES input serial data stream corresponding to the first SER-DES output serial data stream into second SER-DES output signals. The second SER-DES input signals relate to motor drive power outputs or motor control inputs. A serial isolation channel provides a galvanic isolation barrier between the first SER-DES module and the second SER-DES module. The serial isolation channel communicates the first SER-DES output serial data stream across the galvanic isolation barrier to provide the second SER-DES input serial data stream.
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公开(公告)号:US20180278195A1
公开(公告)日:2018-09-27
申请号:US15858485
申请日:2017-12-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Tobias Bernhard Fritz , Martin Staebler , Baher Haroun , Peter Fundaro , Jiri Panacek , Ralf Peter Brederlow
CPC classification number: H02P27/085 , H02M3/157 , H03M9/00 , H04L7/033 , H04L7/06 , H04Q11/02 , H04Q11/04 , H04Q11/06 , H04Q2213/036 , H04Q2213/13036
Abstract: A motor drive circuit includes a first serializer-deserializer (SER-DES) module that converts first SER-DES input signals into a first SER-DES output serial data stream. The first SER-DES input signals relate to motor control inputs or motor drive power outputs. A second SER-DES module converts a second SER-DES input serial data stream corresponding to the first SER-DES output serial data stream into second SER-DES output signals. The second SER-DES input signals relate to motor drive power outputs or motor control inputs. A serial isolation channel provides a galvanic isolation barrier between the first SER-DES module and the second SER-DES module. The serial isolation channel communicates the first SER-DES output serial data stream across the galvanic isolation barrier to provide the second SER-DES input serial data stream.
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公开(公告)号:US10352792B2
公开(公告)日:2019-07-16
申请号:US15649934
申请日:2017-07-14
Applicant: Texas Instruments Incorporated
Inventor: Umidjon Nurmetov , Ralf Peter Brederlow , Baher Haroun
Abstract: An integrated circuit (IC) chip includes a substrate of a piezo-electric material having a first resistivity coefficient associated with a first direction that is longitudinal to a first crystal axis and a second resistivity coefficient associated with a second direction that is transverse to the first crystal axis. The first and second resistivity coefficients have opposite signs. The IC chip also includes a first stress sensing element formed in the substrate and coupled to pass a first current therethrough. The first stress sensing element includes a first resistor aligned such that the major direction of current flow through the first resistor is in the first direction and a second resistor coupled in series with the first resistor and aligned such that the major direction of current flow through the second resistor is in the second direction. A ratio of the resistance of the second resistor to the resistance of the first resistor is equal to a value α, where α is equal to the ratio of the first resistivity coefficient to the second resistivity coefficient.
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公开(公告)号:US20190207786A1
公开(公告)日:2019-07-04
申请号:US15859419
申请日:2017-12-30
Applicant: Texas Instruments Incorporated
Inventor: Swaminathan Sankaran , Bradley Allen Kramer , Baher Haroun , Tobias Bernhard Fritz , Ernst Georg Muellner , Ralf Peter Brederlow
IPC: H04L25/02 , H05K1/02 , H03K17/693 , G01R31/317 , H04B1/525 , H04B3/54
CPC classification number: H04L25/0276 , G01R31/31706 , H03K17/693 , H04B1/525 , H04B3/542 , H05K1/0233
Abstract: Described examples include an integrated circuit including a receive portion to receive an encoded transmission on a line. The receive portion has: a wake mode in which the receiver is capable of receiving the encoded transmission; and a sleep mode in which the receiver is not capable of receiving the encoded transmission. A wakeup controller monitors the line for a wakeup signal and provides a signal to the receive portion to cause the receive portion to enter the wake mode when the wakeup controller receives the wakeup signal.
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公开(公告)号:US20180231424A1
公开(公告)日:2018-08-16
申请号:US15649934
申请日:2017-07-14
Inventor: Umidjon Nurmetov , Ralf Peter Brederlow , Baher Haroun
CPC classification number: G01L1/2293 , G01L1/162 , G01L1/2281 , G01L5/162 , G01L25/006 , H01L22/34 , H01L27/0647 , H01L27/0802 , H01L27/22 , H01L29/84 , H01L29/8605
Abstract: An integrated circuit (IC) chip includes a substrate of a piezo-electric material having a first resistivity coefficient associated with a first direction that is longitudinal to a first crystal axis and a second resistivity coefficient associated with a second direction that is transverse to the first crystal axis. The first and second resistivity coefficients have opposite signs. The IC chip also includes a first stress sensing element formed in the substrate and coupled to pass a first current therethrough. The first stress sensing element includes a first resistor aligned such that the major direction of current flow through the first resistor is in the first direction and a second resistor coupled in series with the first resistor and aligned such that the major direction of current flow through the second resistor is in the second direction. A ratio of the resistance of the second resistor to the resistance of the first resistor is equal to a value α, where α is equal to the ratio of the first resistivity coefficient to the second resistivity coefficient.
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公开(公告)号:US12127480B2
公开(公告)日:2024-10-22
申请号:US16932343
申请日:2020-07-17
Applicant: Texas Instruments Incorporated
Inventor: Umidjon Nurmetov , Ralf Peter Brederlow , Baher Haroun , Jose Antonio Vieira Formenti , Michael Szelong , Tobias Bernhard Fritz
CPC classification number: H10N30/302 , G01L1/18 , G01L1/2268 , H10N30/802
Abstract: In described examples, a circuit includes an analog frontend arranged to generate an analog stress compensating signal in response to a to-be-compensated analog signal and a first-axis stress sensing signal. The analog frontend can comprise a first precision component (e.g., 220) arranged on a piezoelectric material and arranged to generate the to-be-compensated analog signal that is affected by a stress exerted in the piezoelectric material and a directional stress sensor arranged on the piezoelectric material and coupled to the first precision component. The directional stress sensor is arranged to generate the first-axis sensing signal in response to a longitudinal resultant of a stress exerted in the piezoelectric material. A compensating circuit is arranged to generate a compensated output signal in response to the compensating analog signal and to-be-compensated analog signal.
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