公开(公告)号：US20220123130A1

公开(公告)日：2022-04-21

申请号：US17462801

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Ming-Yeh Chuang ,  Abbas Ali

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: A method of fabricating an integrated circuit includes forming and patterning a hardmask over a substrate such that the patterned hardmask exposes regions of the substrate. The exposed regions are etched, thereby forming trenches and a semiconductor fin between the trenches. Prior to removing the hardmask, a photoresist layer is formed and patterned, thereby exposing a section of the semiconductor fin. A dopant is implanted into the exposed section through the hardmask.

公开(公告)号：US11121224B2

公开(公告)日：2021-09-14

申请号：US16270729

申请日：2019-02-08

Applicant: Texas Instruments Incorporated

Inventor： Ming-Yeh Chuang ,  Elizabeth Costner Stewart

IPC: H01L29/40 ,  H01L29/78 ,  H01L21/308 ,  H01L29/66 ,  H01L29/06

Abstract: An integrated circuit (IC) includes a field-plated transistor including a substrate having a semiconductor surface layer, at least one body region in the semiconductor surface layer, and at least a first trench isolation region adjacent to the body region having at least a first tapered sidewall that has an average angle along its full length of 15 to 70 degrees. A gate is over the body region. A field plate is over the first tapered trench isolation region. A source is on one side of the field plate and a drain is on an opposite side of the field plate. The IC also includes circuitry for realizing at least one circuit function having a plurality of transistors which are configured together with the field-plated transistor that utilize second trench isolation regions for isolation that have an average angle of 75 and 90 degrees.

公开(公告)号：US09105567B2

公开(公告)日：2015-08-11

申请号：US13886466

申请日：2013-05-03

Applicant: Texas Instruments Incorporated

Inventor： Ming-Yeh Chuang

IPC: H01L27/02 ,  H01L21/22 ,  H01L29/06 ,  H01L29/861 ,  H01L21/265

CPC classification number: H01L21/22 ,  H01L21/265 ,  H01L27/0255 ,  H01L29/0615 ,  H01L29/0692 ,  H01L29/8611

Abstract: An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said doped area (NWell) and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said doped area (NWell), and said layer (PSD) having a corner in cross-section, and the doping of said doped area (NWell) forming a junction beneath said layer (PSD) with the doping of said doped area (NWell) diluted in a vicinity below the corner of said layer (PSD). Other integrated circuits, substructures, devices, processes of manufacturing, and processes of testing are also disclosed.

Abstract translation: 集成电路结构包括具有第一导电类型的半导体掺杂区域（NWell）和覆盖所述掺杂区域（NWell）的一部分的层（PSD），并且具有与第二导电类型相反的第二类型的导电性的掺杂 所述掺杂区域（NWell）的第一导电类型和具有横截面角的所述层（PSD），以及在所述层（PSD）下面形成结的所述掺杂区域（NWell）的掺杂， 在所述层（PSD）的角下方附近稀释的掺杂区域（NWell）。 还公开了其它集成电路，子结构，器件，制造工艺和测试过程。

公开(公告)号：US20230178372A1

公开(公告)日：2023-06-08

申请号：US17545209

申请日：2021-12-08

Applicant: Texas Instruments Incorporated

Inventor： Bhaskar Srinivasan ,  Walter Scott Idol ,  Ming-Yeh Chuang ,  Brian Goodlin

IPC: H01L21/225 ,  H01L29/66

CPC classification number: H01L21/2251 ,  H01L29/66681 ,  H01L29/66795

Abstract: A fin field-effect transistor (“FinFET”) semiconductor device and method of forming the same. In one example, a semiconductor fin is formed over a semiconductor substrate. A conformal dielectric layer is formed on a top and side surfaces of the fin. A doped semiconductor layer is formed over the conformal dielectric layer, the doped semiconductor layer including a dopant. The doped semiconductor layer is heated thereby driving the dopant through the conformal dielectric layer and forming a doped region of the fin.

公开(公告)号：US20220393021A1

公开(公告)日：2022-12-08

申请号：US17887703

申请日：2022-08-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ming-Yeh Chuang

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/10 ,  H01L29/78

Abstract: A method for fabricating an integrated circuit is disclosed. The method comprises forming a semiconductor ridge over a semiconductor surface of a substrate and forming an implant screen on a top and sidewalls of the semiconductor ridge. The implant screen is at least two times thicker on the top of the semiconductor ridge relative to the sidewalls of the semiconductor ridge. The method further comprises implanting a dopant into the top and sidewalls of the semiconductor ridge.

公开(公告)号：US20210391460A1

公开(公告)日：2021-12-16

申请号：US17409078

申请日：2021-08-23

Applicant: Texas Instruments Incorporated

Inventor： Ming-Yeh Chuang

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/40

Abstract: A semiconductor device includes an extended drain finFET. The drain drift region of the finFET extends between a drain contact region and a body of the finFET. The drain drift region includes an enhanced portion of the drain drift region between the drain contact region and the body. The drain drift region also includes a first charge balance region and a second charge balance region laterally adjacent to, and on opposite sides of, the enhanced portion of the drain drift region. The enhanced portion of the drain drift region and the drain contact region have a first conductivity type; the body, the first charge balance region, and the second charge balance region have a second, opposite, conductivity type. The drain drift region is wider than the body.

公开(公告)号：US10586730B2

公开(公告)日：2020-03-10

申请号：US16010691

申请日：2018-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ming-Yeh Chuang

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/761 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

Abstract: An electronic device includes an isolated region surrounded by an isolation ring over a semiconductor substrate. A well of a first conductivity type is located within the isolated region. A source region and a drain region of a second conductivity type are located over the well. A local-oxidation-of-silicon (LOCOS) layer is located on the well between the source and the drain, between the source and the isolation ring, and between the drain and the isolation ring. A gate electrode located between the source and the drain on said LOCOS layer.

公开(公告)号：US12278290B2

公开(公告)日：2025-04-15

申请号：US17483214

申请日：2021-09-23

Applicant: Texas Instruments Incorporated

Inventor： Ming-Yeh Chuang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: An integrated circuit including a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, and a body region. The source region includes an outer region having a first conductivity type complementary to a second conductivity type of an outer region of the body and an interior-positioned conductive region having the second conductivity type.

公开(公告)号：US20230343828A1

公开(公告)日：2023-10-26

申请号：US17727892

申请日：2022-04-25

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Ming-Yeh Chuang ,  Jingjing Chen

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/74 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L29/7816 ,  H01L29/1095 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/74 ,  H01L29/66681

Abstract: A method of fabricating a transistor includes forming a gate structure over a semiconductor substrate having a first conductivity type. A photoresist layer is patterned over the gate structure to remove the photoresist layer from over an uncovered portion of the gate structure and an adjacent region of the semiconductor substrate abutting the uncovered portion of the gate structure. A deep well region having the first conductivity type is formed using a first dopant such that the first dopant penetrates through the uncovered portion of the gate structure and is blocked by the photoresist layer. A shallow well region is formed by implanting a second dopant such that the second dopant penetrates the adjacent region and is blocked by the uncovered portion of the gate structure.

公开(公告)号：US11658184B2

公开(公告)日：2023-05-23

申请号：US17109244

申请日：2020-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ming-Yeh Chuang

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/762 ,  H01L21/823431 ,  H01L29/402 ,  H01L29/41791 ,  H01L29/7801 ,  H01L29/7851

Abstract: A fin field effect transistor (FinFET) includes a drain region, a merged drift region, and a plurality of fins. The drain region extends above a surface of a semiconductor substrate and has a first dopant concentration of first conductivity type. The merged drift region extends above the substrate surface and touches the drain region, and has a second lower dopant concentration of the first conductivity type. The plurality of fins extend above the substrate surface and each fin is directly connected to the merged drift region. Each fin is connected to a source region having the first conductivity type at a distal end of that fin from the merged drift region.