公开(公告)号：US11515209B2

公开(公告)日：2022-11-29

申请号：US16773692

申请日：2020-01-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhashish Mukherjee ,  Raja Selvaraj ,  Venugopal Gopinathan

IPC: H01L21/78 ,  H01L23/58 ,  H01L23/66 ,  H01L23/18 ,  H01L29/06 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02

Abstract: An example integrated circuit die includes: lower level conductor layers, lower level insulator layers between the lower level conductor layers, lower level vias extending vertically through the lower level insulator layers, upper level conductor layers overlying the lower level conductor layers, upper level insulator layers between and surrounding the upper level conductor layers, upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.

公开(公告)号：US20200161184A1

公开(公告)日：2020-05-21

申请号：US16773692

申请日：2020-01-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhashish Mukherjee ,  Raja Selvaraj ,  Venugopal Gopinathan

IPC: H01L21/78 ,  H01L23/58 ,  H01L23/66 ,  H01L23/18 ,  H01L29/06

Abstract: An example integrated circuit die includes: lower level conductor layers, lower level insulator layers between the lower level conductor layers, lower level vias extending vertically through the lower level insulator layers, upper level conductor layers overlying the lower level conductor layers, upper level insulator layers between and surrounding the upper level conductor layers, upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.

公开(公告)号：US20180026095A1

公开(公告)日：2018-01-25

申请号：US15714682

申请日：2017-09-25

Applicant: Texas Instruments Incorporated

Inventor： Raja Selvaraj ,  Anant Shankar Kamath ,  Byron Lovell Williams ,  Thomas D. Bonifield ,  John Kenneth Arch

IPC: H01L29/06 ,  H01L23/522 ,  H01L49/02 ,  H01L23/00

CPC classification number: H01L29/0646 ,  H01L21/265 ,  H01L21/761 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5286 ,  H01L24/05 ,  H01L27/0676 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2224/48463

Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.