公开(公告)号：US09218981B2

公开(公告)日：2015-12-22

申请号：US14066298

申请日：2013-10-29

Applicant: Texas Instruments Incorporated

Inventor： Gul B. Basim ,  Scott R. Summerfelt ,  Ted S. Moise

IPC: H01L21/30 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/3003 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

Abstract translation: 具有钝化捕获层的集成电路。 具有位于钝化捕获层下面的氢或氘释放层的集成电路。 用于形成具有氢或氘释放层的集成电路的方法。 用于形成具有钝化捕获层的集成电路的方法。

公开(公告)号：US09048297B2

公开(公告)日：2015-06-02

申请号：US14098255

申请日：2013-12-05

Applicant: Texas Instruments Incorporated

Inventor： Scott R. Summerfelt

IPC: H01L21/332 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76885 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5286 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.

Abstract translation: 一种包含垂直互连的集成电路，其包括连续围绕一个或多个介电柱的互连金属区域。 垂直互连电接触下导电结构的顶表面。 上导电结构接触垂直互连的顶表面。 形成集成电路的过程包括形成具有连续围绕一个或多个介电柱的互连金属区域的垂直互连。 垂直互连电接触下导电结构的顶表面，并且上导电结构接触垂直互连的顶表面。

公开(公告)号：US20140370621A1

公开(公告)日：2014-12-18

申请号：US14471240

申请日：2014-08-28

Applicant: Texas Instruments Incorporated

Inventor： Rajni J. Aggarwal ,  Scott R. Summerfelt ,  Gul B. Basim ,  Ted S. Moise

IPC: H01L49/02

CPC classification number: H01L28/57 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

Abstract: An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer.

Abstract translation: 包含铁电电容器，下伏氢屏障和上覆氢阻挡层的集成电路。 一种用于形成包含铁电电容器，下伏氢屏障和上覆氢阻挡层的集成电路的方法。

公开(公告)号：US20140308762A1

公开(公告)日：2014-10-16

申请号：US14316114

申请日：2014-06-26

Applicant: Texas Instruments Incorporated

Inventor： Scott R. Summerfelt ,  Robert G. Fleck

IPC: H01L21/66

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F2217/12 ,  H01L22/26 ,  H01L27/0207 ,  H01L27/11507 ,  Y02P90/265

Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the subregion (208).

Abstract translation: 公开了一种在衬底上放置虚拟填充层的方法（图2）。 该方法包括识别衬底（210）的子区域。 确定子区域中的层的密度（212）。 选择虚拟填充层的图案以产生预定的密度（216）。 所选择的图案被放置在子区域（208）中。

公开(公告)号：US20140215425A1

公开(公告)日：2014-07-31

申请号：US14230847

申请日：2014-03-31

Applicant: Texas Instruments Incorporated

Inventor： Scott R. Summerfelt ,  Robert G. Fleck

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F2217/12 ,  H01L22/26 ,  H01L27/0207 ,  H01L27/11507 ,  Y02P90/265

Abstract: A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).

Abstract translation: 公开了一种在衬底上放置虚拟填充层的方法（图2）。 该方法包括识别衬底（210）的子区域。 确定子区域中的层的密度（212）。 选择虚拟填充层的图案以产生预定的密度（216）。 所选择的图案被放置在子区域（208）中。

公开(公告)号：US08778700B2

公开(公告)日：2014-07-15

申请号：US13770781

申请日：2013-02-19

Applicant: Texas Instruments Incorporated

Inventor： Kezhakkedath R. Udayakumar ,  Scott R. Summerfelt ,  Ted S. Moise ,  Manoj K. Jain

IPC: H01L21/00 ,  H01L21/82 ,  H01L21/4763 ,  H01L21/768 ,  H01L49/02 ,  H01L27/115

CPC classification number: H01L21/76843 ,  H01L27/11509 ,  H01L28/57

Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.

Abstract translation: 包含FeCap阵列的集成电路。 FeCap阵列在侧面至少部分地被氢阻挡壁包围，并且在顶部被氢阻挡顶板包围。 一种用于至少部分地封闭具有氢阻挡壁和氢阻挡顶板的FeCap阵列的方法。

公开(公告)号：US20140051234A1

公开(公告)日：2014-02-20

申请号：US14066298

申请日：2013-10-29

Applicant: Texas Instruments Incorporated

Inventor： Gul B. Basim ,  Scott R. Summerfelt ,  Ted S. Moise

IPC: H01L21/30

CPC classification number: H01L21/3003 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

Abstract translation: 具有钝化捕获层的集成电路。 具有位于钝化捕获层下面的氢或氘释放层的集成电路。 用于形成具有氢或氘释放层的集成电路的方法。 用于形成具有钝化捕获层的集成电路的方法。

公开(公告)号：US20130164933A1

公开(公告)日：2013-06-27

申请号：US13770781

申请日：2013-02-19

Applicant: Texas Instruments Incorporated

Inventor： Kezhakkedath R. Udayakumar ,  Scott R. Summerfelt ,  Ted S. Moise ,  Manoj K. Jain

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L27/11509 ,  H01L28/57

Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.

Abstract translation: 包含FeCap阵列的集成电路。 FeCap阵列在侧面至少部分地被氢阻挡壁包围，并且在顶部被氢阻挡顶板包围。 一种用于至少部分地封闭具有氢阻挡壁和氢阻挡顶板的FeCap阵列的方法。