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公开(公告)号：US20190339806A1
公开(公告)日：2019-11-07
申请号：US16512020
申请日：2019-07-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Wei-Yan Shih , Steve Kummerl , Mark Stephen Toth , Alok Lohia , Terry Lee Sculley , Seung Bae Lee , Scott Robert Summerfelt
IPC: G06F3/041
Abstract: An integrated force sensing element includes a piezoelectric sensor formed in an integrated circuit (IC) chip and a strain gauge at least partially overlying the piezoelectric sensor, where the piezoelectric sensor is able to flex. A human-machine interface using the integrated force sensing element is also disclosed and may include a conditioning circuit, temperature gauge, FRAM and a processor core.
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公开(公告)号：US10353503B2
公开(公告)日：2019-07-16
申请号：US14926265
申请日：2015-10-29
Applicant: Texas Instruments Incorporated
Inventor： Wei-Yan Shih , Steve Kummerl , Mark Stephen Toth , Alok Lohia , Terry Lee Sculley , Seung Bae Lee , Scott Robert Summerfelt
IPC: G06F3/041
Abstract: An integrated force sensing element includes a piezoelectric sensor formed in an integrated circuit (IC) chip and a strain gauge at least partially overlying the piezoelectric sensor, where the piezoelectric sensor is able to flex. A human-machine interface using the integrated force sensing element may include a conditioning circuit, temperature gauge, FRAM and a processor core.
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13.发明授权Dual comparator-based error correction scheme for analog-to-digital converters 有权用于模数转换器的基于双比较器的纠错方案公开(公告)号：US09148159B1
公开(公告)日：2015-09-29
申请号：US14209813
申请日：2014-03-13
Applicant: Texas Instruments Incorporated
Inventor： Ajit Sharma , Seung Bae Lee , Srinath M. Ramaswamy , Sriram Narayanan , Arup Polley
CPC classification number: H03M1/0678 , H03M1/00 , H03M1/12 , H03M1/468
Abstract: An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC.
Abstract translation: 模数转换器（ADC）包括第一比较器，第二比较器和判定定时比较逻辑单元。 第一比较器被配置为输出第一输出电压，并且第二比较器被配置为在ADC的相同的二进制算法迭代期间输出第二输出电压。 所述判定定时比较逻辑单元被配置为识别所述第一输出电压的第一极性和所述第二输出电压的第二极性，并且如果所述第一极性等于第二极性，则将至少一个冗余电容器插入下一个 ADC的二进制算法迭代。
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14.发明申请DUAL COMPARATOR-BASED ERROR CORRECTION SCHEME FOR ANALOG-TO-DIGITAL CONVERTERS 有权用于模拟数字转换器的双基于比较器的错误校正方案公开(公告)号：US20150263744A1
公开(公告)日：2015-09-17
申请号：US14209813
申请日：2014-03-13
Applicant: Texas Instruments Incorporated
Inventor： Ajit Sharma , Seung Bae Lee , Srinath M. Ramaswamy , Sriram Narayanan , Arup Polley
CPC classification number: H03M1/0678 , H03M1/00 , H03M1/12 , H03M1/468
Abstract: An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC.
Abstract translation: 模数转换器（ADC）包括第一比较器，第二比较器和判定定时比较逻辑单元。 第一比较器被配置为输出第一输出电压，并且第二比较器被配置为在ADC的相同二进制算法迭代期间输出第二输出电压。 所述判定定时比较逻辑单元被配置为识别所述第一输出电压的第一极性和所述第二输出电压的第二极性，并且如果所述第一极性等于第二极性，则将至少一个冗余电容器插入下一个 ADC的二进制算法迭代。
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