公开(公告)号：US11474151B2

公开(公告)日：2022-10-18

申请号：US17138529

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Prasanth Viswanathan Pillai ,  Rajeev Suvarna ,  Saya Goud Langadi ,  Shailesh Ganapat Ghotgalkar

IPC: H03K3/00 ,  G01R31/3177 ,  H03K5/24 ,  H03K19/003 ,  H03K3/037

Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

公开(公告)号：US11444626B2

公开(公告)日：2022-09-13

申请号：US17458001

申请日：2021-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das ,  Jiankun Hu

IPC: H03L7/089 ,  H03L7/095 ,  H03L7/087

Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.

公开(公告)号：US11385862B2

公开(公告)日：2022-07-12

申请号：US17068969

申请日：2020-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shailesh Ganapat Ghotgalkar

IPC: G06F5/14 ,  G06F3/06 ,  G06F5/06

Abstract: A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.

公开(公告)号：US11239847B2

公开(公告)日：2022-02-01

申请号：US16940880

申请日：2020-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das

IPC: H03L7/087 ,  H03L7/099

Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.

公开(公告)号：US20210026597A1

公开(公告)日：2021-01-28

申请号：US17068969

申请日：2020-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shailesh Ganapat Ghotgalkar

IPC: G06F5/14 ,  G06F3/06 ,  G06F5/06

Abstract: A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.

公开(公告)号：US20190310825A1

公开(公告)日：2019-10-10

申请号：US16390780

申请日：2019-04-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shailesh Ganapat Ghotgalkar

IPC: G06F5/14 ,  G06F5/06 ,  G06F3/06

Abstract: A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.

公开(公告)号：US10268448B2

公开(公告)日：2019-04-23

申请号：US15148325

申请日：2016-05-06

Applicant: Texas Instruments Incorporated

Inventor： Shailesh Ganapat Ghotgalkar

IPC: G06F3/06 ,  G06F5/06 ,  G06F5/14

Abstract: A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.

公开(公告)号：US20250103244A1

公开(公告)日：2025-03-27

申请号：US18371338

申请日：2023-09-21

Applicant: Texas Instruments Incorporated

Inventor： Vignesh Raghavendra ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Sai Karthik Rajaraman ,  Shailesh Ganapat Ghotgalkar ,  Mohammad Asif Farooqui

IPC: G06F3/06

Abstract: An example apparatus includes a read queue to store a first read request to access a first storage, sequencing circuitry coupled to the read queue, and prioritization circuitry coupled to the sequencing circuitry and coupled to the first storage and a second storage via a shared bus. The example sequencing circuitry is to sequence a portion of a second request to access the second storage to be interleaved with a wait interval of the first read request, the second request queued after the first read request. Additionally, the example prioritization circuitry is to generate a first transaction to access the first storage over the shared bus and a second transaction to access the second storage over the shared bus concurrently with the first transaction, the first transaction based on the first read request, the second transaction based on the second request.

公开(公告)号：US20240267051A1

公开(公告)日：2024-08-08

申请号：US18638065

申请日：2024-04-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das

IPC: H03L7/087 ,  H03L7/099

CPC classification number: H03L7/087 ,  H03L7/099

Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.

公开(公告)号：US12025659B2

公开(公告)日：2024-07-02

申请号：US18047511

申请日：2022-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prasanth Viswanathan Pillai ,  Rajeev Suvarna ,  Saya Goud Langadi ,  Shailesh Ganapat Ghotgalkar

IPC: G06F3/06 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/3187 ,  G06F11/10 ,  G06F12/0804 ,  G06F13/16 ,  H03K3/037 ,  H03K5/24 ,  H03K19/003

CPC classification number: G01R31/3177 ,  G01R31/3187 ,  H03K3/037 ,  H03K5/24 ,  H03K19/003 ,  G01R31/318566

Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.