Abstract:
An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC.
Abstract:
A method is provided. A first edge on a first gating signal is generated, and a local oscillator and a shared clocking circuit with the first edge on the first gating signal. A second edge on a second gating signal is generated following the first edge on the first gating signal, and a receiver circuit is activated with the second edge on the second gating signal, where the receiver circuit includes a mixer. A transmit pulse following the first edge on the first gating signal is generated with the transmit pulse having a third edge. A switch that short circuits outputs of the mixer is then released following the later of the third edge of the transmit pulse and a delay.
Abstract:
An apparatus is provided. Transmission line cells are formed in a first region. A first metallization layer is formed over the transmission line cells within a portion of the first region. At least a portion of the first metallization layer is electrically coupled to the plurality of transmission line cells. A second metallization layer is formed over the first metallization layer with an interconnect portion, and overlay portion, and a first balun. The interconnect portion at least partially extends into the first region, and the overlay portion is within the first region. The first balun winding is electrically coupled to the overlay portion and partially extends into a second region. The first region partially surrounds the second region. A third metallization layer is formed over the second metallization layer having a second balun winding within the second region, where the second winding is generally coaxial with the first balun winding.
Abstract:
A method is provided. A first edge on a first gating signal is generated, and a local oscillator and a shared clocking circuit with the first edge on the first gating signal. A second edge on a second gating signal is generated following the first edge on the first gating signal, and a receiver circuit is activated with the second edge on the second gating signal, where the receiver circuit includes a mixer. A transmit pulse following the first edge on the first gating signal is generated with the transmit pulse having a third edge. A switch that short circuits outputs of the mixer is then released following the later of the third edge of the transmit pulse and a delay.
Abstract:
A transducer system with a transducer and circuitry for applying a waveform to excite the transducer during an excitation period. The applying circuitry also comprises circuitry for changing a frequency of the waveform during the excitation period.
Abstract:
An amplifier includes a graphene Hall sensor (GHS). The GHS includes a graphene layer formed above a substrate, a dielectric structure formed above a channel portion of the graphene layer, and a conductive gate structure formed above at least a portion of the dielectric structure above the channel portion of the graphene layer for applying a gate voltage. The GHS also includes first and second conductive excitation contact structures coupled with corresponding first and second excitation portions of the graphene layer for applying at least one of the following to the channel portion of the graphene layer: a bias voltage; and a bias current. The GHS further includes first and second conductive sense contact structures coupled with corresponding first and second sense portions of the graphene layer. The amplifier also includes a current sense amplifier (CSA) coupled to the GHS. The CSA senses current output from the GHS.
Abstract:
A system comprises first and second Hall-effect sensors and an amplifier. The first Hall-effect sensor has a first bias current direction parallel to a first direction, a pair of first bias input terminals spaced along the first direction, and a pair of first sense output terminals spaced along an orthogonal second direction. The second Hall-effect sensor has a second bias current direction parallel to the second direction, a pair of second bias input terminals spaced along the second direction, and a pair of second sense output terminals connected out of phase with the first sense terminals. The amplifier has a pair of amplifier input terminals coupled to the first and second sense terminals.
Abstract:
A Hall sensor circuit includes a first Hall sensor, a second Hall sensor, a first preamplifier circuit, a second preamplifier circuit, a subtractor circuit, and a duty cycling circuit. The first preamplifier circuit includes an input and an output. The input is coupled to the first Hall sensor. The second preamplifier circuit includes a first input, a second input, and an output. The first input is coupled to the second Hall sensor. The subtractor circuit includes a first input coupled to the output of the first preamplifier circuit, a second input coupled to the output of the second preamplifier circuit, and an output coupled to the second input of the second preamplifier circuit. The duty cycling circuit is coupled to the second preamplifier circuit and the second Hall sensor.
Abstract:
A system includes a first amplifier and a first Hall sensor group coupled to the first amplifier. The system includes a second amplifier and a second Hall sensor group coupled to the second amplifier, where the second Hall sensor group includes a spinning Hall group. The system includes a first demodulator, where the first demodulator input is coupled to the first amplifier output. The system includes a second demodulator, where the second demodulator input is coupled to the second amplifier output. The system also includes a subtractor, the first subtractor input coupled to the first demodulator output, and the second subtractor input coupled to the second demodulator output. The system includes a filter coupled to the subtractor output and to a second input of the first amplifier, and a calibration module coupled to the subtractor output.
Abstract:
A technique for removing the background from a transmission spectrum including determining performance characteristics of a detector, measuring a transmission spectrum that includes an absorption line, determining performance characteristics of a gas cell, and removing a background spectrum from the transmission spectrum by combining the transmission spectrum with the performance characteristics of the detector and the performance characteristics of the gas cell.