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    Integrated clock gating cell using a low area and a low power latch
    11.
    发明授权
    Integrated clock gating cell using a low area and a low power latch 有权
    集成时钟门控单元使用低面积和低功率锁存

    公开(公告)号：US09246489B1

    公开(公告)日：2016-01-26

    申请号：US14499745

    申请日：2014-09-29

    Applicant: Texas Instruments Incorporated

    Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

    IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/096 ,  H03K5/135 ,  H03K3/037

    CPC classification number: H03K19/0013 ,  H03K3/012 ,  H03K3/356173 ,  H03K5/135 ,  H03K19/0002 ,  H03K19/0016 ,  H03K19/01855 ,  H03K19/0966

    Abstract: The disclosure provides an ICG (integrated clock gating) cell that utilizes a low area and a low power latch. The ICG cell includes a first logic gate that receives an enable signal and generates a latch input. A latch is coupled to the first logic gate and receives the latch input and a clock input. The latch includes a tri-state inverter and an inverting logic gate. The tri-state inverter is activated by a control signal generated by the inverting logic gate. A second logic gate receives the control signal and generates a gated clock.

    Abstract translation: 本公开提供了利用低面积和低功率锁存器的ICG（集成时钟门控）单元。 ICG单元包括接收使能信号并产生锁存输入的第一逻辑门。 锁存器耦合到第一逻辑门并接收锁存器输入和时钟输入。 锁存器包括三态反相器和反相逻辑门。 三态反相器由反相逻辑门产生的控制信号激活。 第二逻辑门接收控制信号并产生门控时钟。

    Reduced area, reduced power flip-flop
    12.
    发明授权
    Reduced area, reduced power flip-flop 有权

    公开(公告)号：US11043937B1

    公开(公告)日：2021-06-22

    申请号：US16713343

    申请日：2019-12-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Badarish Mohan Subbannavar ,  Arnab Khawas ,  Suvam Nandi

    IPC: H03K3/037 ,  H03K3/012

    Abstract: A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.

    Transformation based filter for interpolation or decimation
    13.
    发明授权
    Transformation based filter for interpolation or decimation 有权

    公开(公告)号：US10090866B2

    公开(公告)日：2018-10-02

    申请号：US15395135

    申请日：2016-12-30

    Applicant: Texas Instruments Incorporated

    Inventor： Jaiganesh Balakrishnan ,  Suvam Nandi ,  Sundarrajan Rangachari

    IPC: G06F17/17 ,  H04B1/00 ,  H04B1/04 ,  H04B1/10 ,  G06F5/01 ,  H03H17/02

    Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.

    Low area full adder with shared transistors
    14.
    发明授权
    Low area full adder with shared transistors 有权
    具有共享晶体管的低面积全加器

    公开(公告)号：US09471278B2

    公开(公告)日：2016-10-18

    申请号：US14496767

    申请日：2014-09-25

    Applicant: Texas Instruments Incorporated

    Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

    IPC: G06F7/501 ,  G06F7/50 ,  H03K19/20 ,  H03K19/00

    CPC classification number: G06F7/50 ,  G06F7/501 ,  H03K19/0013 ,  H03K19/20

    Abstract: A full adder is disclosed that utilizes low area. The full adder includes an exclusive NOR logic circuit. The exclusive NOR logic circuit receives a first input and a second input. A first inverter receives an output of the exclusive NOR logic circuit and generates an exclusive OR output. A carry generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and a third input. The carry generation circuit generates an inverted carry. A second inverter is coupled to the carry generation circuit and generates a carry on receiving the inverted carry. A sum generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and the third input. The sum generation circuit generates an inverted sum. A third inverter is coupled to the sum generation circuit and generates a sum on receiving the inverted sum.

    Abstract translation: 公开了一种利用低面积的全加器。 全加器包括一个异或逻辑电路。 异或逻辑电路接收第一输入和第二输入。 第一反相器接收异或逻辑电路的输出并产生异或输出。 进位发生电路接收异或逻辑电路的输出，异或输出和第三输入。 进位发生电路产生反转进位。 第二反相器耦合到进位发生电路，并产生接收反向进位的进位。 和产生电路接收异或逻辑电路的输出，异或输出和第三输入。 和产生电路产生一个反相和。 第三反相器耦合到和产生电路，并在接收到反相和时产生和。

    FLIP-FLOPS WITH LOW CLOCK POWER
    15.
    发明申请
    FLIP-FLOPS WITH LOW CLOCK POWER 有权
    具有低时钟功率的FLIP-FLOPS

    公开(公告)号：US20160094204A1

    公开(公告)日：2016-03-31

    申请号：US14498412

    申请日：2014-09-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

    IPC: H03K3/012 ,  H03K3/037

    CPC classification number: H03K3/012 ,  H03K3/0372

    Abstract: The disclosure provides a flip-flop that utilizes low power as a result of reduced transistor count. The flip-flop includes a tri-state inverter that receives a flip-flop input and a clock input. A master latch is coupled to an output of the tri-state inverter and provides a control signal to the tri-state inverter. The control signal activates the tri-state inverter. A slave latch receives an output of the master latch and the control signal. An output inverter is coupled to an output of the slave latch and generates a flip-flop output.

    Abstract translation: 本公开提供了一种触发器，其由于晶体管数量减少而利用低功率。 触发器包括接收触发器输入和时钟输入的三态反相器。 主锁存器耦合到三态反相器的输出，并向三态反相器提供控制信号。 控制信号激活三态变频器。 从锁存器接收主锁存器和控制信号的输出。 输出反相器耦合到从锁存器的输出并产生触发器输出。

    Internally truncated multiplier
    16.
    发明授权
    Internally truncated multiplier 有权

    公开(公告)号：US11029919B2

    公开(公告)日：2021-06-08

    申请号：US16852710

    申请日：2020-04-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jawaharlal Tangudu ,  Suvam Nandi ,  Pooja Sundar ,  Jaiganesh Balakrishnan

    IPC: G06F7/523 ,  G06F7/50 ,  H03D7/16

    Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.

    Digital down converter
    17.
    发明授权
    Digital down converter 有权

    公开(公告)号：US10666293B2

    公开(公告)日：2020-05-26

    申请号：US15960591

    申请日：2018-04-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jawaharlal Tangudu ,  Suvam Nandi ,  Jaiganesh Balakrishnan

    IPC: H03M7/00 ,  H03M7/30 ,  H03H17/06 ,  H03D7/16

    Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.

    INTERNALLY TRUNCATED MULTIPLIER
    18.
    发明申请
    INTERNALLY TRUNCATED MULTIPLIER 审中-公开

    公开(公告)号：US20190317731A1

    公开(公告)日：2019-10-17

    申请号：US16454369

    申请日：2019-06-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jawaharlal Tangudu ,  Suvam Nandi ,  Pooja Sundar ,  Jaiganesh Balakrishnan

    IPC: G06F7/523 ,  G06F7/50 ,  H03D7/16

    Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.

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