公开(公告)号：US20190190521A1

公开(公告)日：2019-06-20

申请号：US16284212

申请日：2019-02-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Erkan Bilhan ,  Venkateswara Reddy Pothireddy

IPC: H03K19/0175

CPC classification number: H03K19/017509 ,  H03K3/037

Abstract: A method and circuitry that enables an input/output pin (I/O) on a System on a Chip to function either as an analog or as a digital input/output without compromising the overall performance of the system, thus giving the automated test equipment full flexibility to maximize parallel testing for both analog and digital modules.

公开(公告)号：US10256821B2

公开(公告)日：2019-04-09

申请号：US15437593

申请日：2017-02-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Erkan Bilhan ,  Venkateswara Reddy Pothireddy

IPC: H03K19/017 ,  H03K19/0175 ,  H03K3/037

Abstract: A method and circuitry that enables an input/output pin (I/O) on a System on a Chip to function either as an analog or as a digital input/output without compromising the overall performance of the system, thus giving the automated test equipment full flexibility to maximize parallel testing for both analog and digital modules.

公开(公告)号：US20180183434A1

公开(公告)日：2018-06-28

申请号：US15387683

申请日：2016-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Erkan Bilhan ,  Sumant Dinkar Kale ,  Chunhua Hu

IPC: H03K17/22 ,  H03B5/32

CPC classification number: H03K17/22 ,  G06F11/1441 ,  H03B5/32

Abstract: A functional safety Power on Reset system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. A plurality of voltage monitoring stages is implemented to ensure redundancy.

公开(公告)号：US12158836B2

公开(公告)日：2024-12-03

申请号：US18305873

申请日：2023-04-24

Applicant: Texas Instruments Incorporated

Inventor： Venkateswar Reddy Kowkutla ,  Rejitha Nair

IPC: G06F11/36 ,  G01R31/317

Abstract: An integrated circuit includes a processor core configured to perform boot operations; and a microcontroller coupled to a processor core. The microcontroller includes: a set of microcontroller components; and a state machine coupled to the set of microcontroller components. The state machine is configured to perform self-test operations on the set of microcontroller components before the boot operations.

公开(公告)号：US20240178832A1

公开(公告)日：2024-05-30

申请号：US18432430

申请日：2024-02-05

Applicant: Texas Instruments Incorporated

Inventor： Venkateswar Reddy Kowkutla ,  Chunhua Hu ,  Erkan Bilhan ,  Sumant Dinkar Kale

IPC: H03K17/22 ,  G05B19/042 ,  G06F1/24 ,  G06F1/3296 ,  H03K17/30

CPC classification number: H03K17/22 ,  G05B19/042 ,  G06F1/24 ,  G06F1/3296 ,  G05B2219/21119 ,  H03K17/30

Abstract: Systems and methods are provided for voltage monitoring and reset sequencing. One such system includes a voltage detector including multiple voltage level detectors to output multiple power OK signals, respectively; a trim adjustment circuit to output multiple trim values to the multiple voltage level detectors, respectively; and a sequencer circuit coupled to the trim adjustment circuit and the voltage detector. In response to receiving the power OK signals from the multiple voltage level detectors, the sequencer circuit controls output of a reset signal to a target voltage domain.

公开(公告)号：US11923836B2

公开(公告)日：2024-03-05

申请号：US16912057

申请日：2020-06-25

Applicant: Texas Instruments Incorporated

Inventor： Venkateswar Reddy Kowkutla ,  Chunhua Hu ,  Erkan Bilhan ,  Sumant Dinkar Kale

IPC: H03K17/22 ,  G05B19/042 ,  G06F1/24 ,  G06F1/3296 ,  H03K17/30

CPC classification number: H03K17/22 ,  G05B19/042 ,  G06F1/24 ,  G06F1/3296 ,  G05B2219/21119 ,  H03K17/30

Abstract: An example includes a circuit including a first AND gate including a first input terminal, a second input terminal, and an output terminal, a second AND gate including a first input terminal, a second input terminal, and an output terminal, and a third AND gate including a first input terminal, a second input terminal, and an output terminal. The circuit also includes an OR gate including a first input terminal coupled to the output terminal of the first AND gate, a second input terminal coupled to the output terminal of the second AND gate, a third input terminal coupled to the output terminal of the third AND gate, and an output terminal.

公开(公告)号：US20210044292A1

公开(公告)日：2021-02-11

申请号：US17080239

申请日：2020-10-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua Hu ,  Venkateswar Reddy Kowkutla ,  Charles Fuoco

IPC: H03K17/22

Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.

公开(公告)号：US20190212794A1

公开(公告)日：2019-07-11

申请号：US16299544

申请日：2019-03-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua Hu ,  Venkateswar Reddy Kowkutla ,  Charles Fuoco

IPC: G06F1/24 ,  G06F1/28 ,  G06F11/22

CPC classification number: G06F1/24 ,  G06F1/28 ,  G06F11/22

Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.

公开(公告)号：US10228736B2

公开(公告)日：2019-03-12

申请号：US15395156

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua Hu ,  Venkateswar Reddy Kowkutla ,  Charles Fuoco

IPC: G06F1/24

Abstract: The reset isolation mechanism describes an embedded safety island inside a system on a chip which reduces the overall system cost while achieving functional safety. The safety island ensures an orderly shutdown of all or part of the rest of the system on a chip without the possibility of a safety island hang due to incomplete transactions at the time of the reset.

公开(公告)号：US10050617B2

公开(公告)日：2018-08-14

申请号：US15387683

申请日：2016-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Erkan Bilhan ,  Sumant Dinkar Kale ,  Chunhua Hu

IPC: H03K17/22 ,  H03B5/32

CPC classification number: H03K17/22 ,  H03B5/32

Abstract: A functional safety Power on Reset system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. A plurality of voltage monitoring stages is implemented to ensure redundancy.