公开(公告)号：US20140078819A1

公开(公告)日：2014-03-20

申请号：US14083637

申请日：2013-11-19

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh ,  Anand Seshardi ,  Zhonghai Shi

IPC: G11C11/413

CPC classification number: G11C11/413 ,  G11C11/412 ,  H01L27/1104

Abstract: Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.

Abstract translation: 在具有不对称上下文（例如缓冲电路）的静态随机存取存储器（SRAM）单元中的平衡电性能。 每个存储单元包括诸如读缓冲器的电路特征，其具有比单元内的其它晶体管更大的晶体管尺寸和特征，并且其中特征不对称影响较小单元晶体管。 为了获得最佳性能，单元晶体管对将彼此电气匹配。 更接近不对称特征的单元晶体管中的一个或多个不同地构成，例如具有不同的沟道宽度，沟道长度或净沟道掺杂剂浓度，以补偿不对称特征的邻近效应。

公开(公告)号：US20130343136A1

公开(公告)日：2013-12-26

申请号：US14010881

申请日：2013-08-27

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/41 ,  G11C29/022

Abstract: An SRAM with buffered-read bit cells is disclosed (FIGS. 1-6). The integrated circuit includes a plurality of memory cells (102). Each memory cell has a plurality of transistors (200, 202). A first memory cell (FIG. 2) is arranged to store a data signal in response to an active write word line (WWL) and to produce the data signal in response to an active read word line (RWL). A test circuit (104) formed on the integrated circuit is operable to test current and voltage characteristics of each transistor of the plurality of transistors of the first memory cell (FIGS. 7-10).

Abstract translation: 公开了具有缓冲读位元的SRAM（图1-6）。 集成电路包括多个存储单元（102）。 每个存储单元具有多个晶体管（200,202）。 第一存储器单元（图2）被布置为响应于有效写入字线（WWL）存储数据信号，并且响应于有源读取字线（RWL）产生数据信号。 形成在集成电路上的测试电路（104）可操作以测试第一存储单元的多个晶体管中每个晶体管的电流和电压特性（图7-10）。

公开(公告)号：US09466356B2

公开(公告)日：2016-10-11

申请号：US14814798

申请日：2015-07-31

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: G11C11/417 ,  G11C11/419 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  G11C11/41

CPC classification number: G11C11/417 ,  G11C11/41 ,  G11C11/419 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  G11C2029/5002

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

公开(公告)号：US09208832B2

公开(公告)日：2015-12-08

申请号：US13723639

申请日：2012-12-21

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Yang Yi ,  Wah Kit Loh

IPC: G11C5/14 ,  G11C29/50 ,  G11C29/02 ,  G11C29/12 ,  G11C29/26 ,  G11C11/41 ,  G11C29/40 ,  G11C29/04

CPC classification number: G11C5/147 ,  G11C11/41 ,  G11C29/021 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/40 ,  G11C29/50004 ,  G11C2029/0401

Abstract: A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed.

Abstract translation: 一种测试包括多个存储器阵列实例的大规模集成电路的方法，以及用于辅助这种测试的集成电路结构。 在一个实施例中，通过提取布局参数和随后的电路模拟来确定阵列偏置导体中的寄生电阻引起的电压降，其导出每个存储器阵列操作期间那些导体中的电压降。 在另一个实施例中，来自每个存储器阵列的感测线选择性地连接到集成电路的测试感测端子，在该测试检测端子处外部测量每个存储器阵列处的阵列偏置电压。 可以进行施加电压的反馈控制以达到期望的阵列偏置电压。

公开(公告)号：US20150348615A1

公开(公告)日：2015-12-03

申请号：US14814750

申请日：2015-07-31

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: G11C11/419 ,  G11C29/08

CPC classification number: G11C11/417 ,  G11C11/41 ,  G11C11/419 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  G11C2029/5002

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

公开(公告)号：US09093315B2

公开(公告)日：2015-07-28

申请号：US14099973

申请日：2013-12-08

Applicant: Texas Instruments Incorporated

Inventor： Shaofeng Yu ,  Russell Carlton McMullan ,  Wah Kit Loh

IPC: H01L29/08 ,  H01L27/11 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0847

Abstract: An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.

Abstract translation: 包含SAR SRAM和CMOS逻辑的集成电路，其中SAR SRAM单元的栅极延伸上的侧壁间隔物比逻辑PMOS栅极上的侧壁间隔更薄，使得漏极节点SRAM PSD层的深度保持在 伸展接触。 形成包含SAR SRAM和CMOS逻辑的集成电路的过程，包括选择性地蚀刻在SAR SRAM单元的栅极延伸上的侧壁间隔物，使得漏极节点SRAM PSD层的深度保持在拉伸接触下 。 形成包含SAR SRAM和CMOS逻辑的集成电路的过程，包括在漏极节点SRAM PSD层中选择性地注入额外的p型掺杂剂，使得漏极节点SRAM PSD层的深度保持在拉伸接触下。

公开(公告)号：US08472229B2

公开(公告)日：2013-06-25

申请号：US13655512

申请日：2012-10-19

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh ,  Anand Seshadri ,  Terence G. W. Blake

IPC: G11C5/02 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  G11C5/025 ,  Y02P90/265

Abstract: An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array.

Abstract translation: 一种用于生成集成电路的布局的集成电路和方法，其中根据类似于单元本身构造的器件在一个或多个结构级别中实现诸如存储器或逻辑单元的重复特征阵列的外围电路。 确定在各种水平上引起邻近效应的距离。 这些接近效应距离决定了在每个级别的阵列之外和之后重复的那些特征的数量，其中构造外围电路以匹配阵列中的重复特征的构造。

公开(公告)号：US09805788B2

公开(公告)日：2017-10-31

申请号：US14814750

申请日：2015-07-31

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: G11C11/417 ,  G11C29/00 ,  G11C11/419 ,  G11C29/08 ,  G11C29/50 ,  G11C11/41

CPC classification number: G11C11/417 ,  G11C11/41 ,  G11C11/419 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  G11C2029/5002

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

公开(公告)号：US20150340084A1

公开(公告)日：2015-11-26

申请号：US14814785

申请日：2015-07-31

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: G11C11/419 ,  G11C29/00

CPC classification number: G11C11/417 ,  G11C11/41 ,  G11C11/419 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  G11C2029/5002

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

公开(公告)号：US20140346609A1

公开(公告)日：2014-11-27

申请号：US14099973

申请日：2013-12-08

Applicant: Texas Instruments Incorporated

Inventor： Shaofeng Yu ,  Russell Carlton McMullan ,  Wah Kit Loh

IPC: H01L27/11 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0847

Abstract: An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.

Abstract translation: 包含SAR SRAM和CMOS逻辑的集成电路，其中SAR SRAM单元的栅极延伸上的侧壁间隔物比逻辑PMOS栅极上的侧壁间隔更薄，使得漏极节点SRAM PSD层的深度保持在 伸展接触。 形成包含SAR SRAM和CMOS逻辑的集成电路的过程，包括选择性地蚀刻在SAR SRAM单元的栅极延伸上的侧壁间隔物，使得漏极节点SRAM PSD层的深度保持在拉伸接触下 。 形成包含SAR SRAM和CMOS逻辑的集成电路的过程，包括在漏极节点SRAM PSD层中选择性地注入额外的p型掺杂剂，使得漏极节点SRAM PSD层的深度保持在拉伸接触下。