公开(公告)号：US20180269390A1

公开(公告)日：2018-09-20

申请号：US15707028

申请日：2017-09-18

Applicant: Toshiba Memory Corporation

Inventor： Masumi SAITOH ,  Takayuki Ishikawa ,  Takashi Tachikawa ,  Marina Yamaguchi

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/085 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/147 ,  H01L45/1616 ,  H01L45/1641

Abstract: A memory device according to an embodiment includes a first conductive layer, a second conductive layer; and a first metal oxide layer provided between the first conductive layer and the second conductive layer. The first metal oxide layer includes titanium oxide, the first metal oxide layer has a first region and a second region, a mole fraction of anatase titanium oxide in the titanium oxide of the first region is a first mole fraction, and a mole fraction of anatase titanium oxide in the titanium oxide of the second region is a second mole fraction lower than the first mole fraction.

公开(公告)号：US20200027923A1

公开(公告)日：2020-01-23

申请号：US16299660

申请日：2019-03-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Toshiya MURAKAMI ,  Akihiro KAJITA ,  Masumi SAITOH

IPC: H01L27/24 ,  H01L45/00

Abstract: According to one embodiment, a memory device includes first and second electrically conductive portions, a first variable resistance portion, and a first region. A direction from the first electrically conductive portion toward the second electrically conductive portion is aligned with a first direction. The first variable resistance portion is provided between the first and second electrically conductive portions. A second direction from the first variable resistance portion toward the first region crosses the first direction. The first region includes a first layer portion, and a second layer portion provided between the first layer portion and the first variable resistance portion in the second direction. A first distance between the first and second layer portions is longer than first or second lattice length. The first lattice length is a lattice length of the first layer portion. The second lattice length is a lattice length of the second layer portion.

公开(公告)号：US20190096481A1

公开(公告)日：2019-03-28

申请号：US15910408

申请日：2018-03-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Chika TANAKA ,  Masumi SAITOH

IPC: G11C13/00 ,  H01L23/528 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/0007 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  G11C2213/79 ,  H01L23/528 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1683

Abstract: A semiconductor memory device includes a substrate, a stacked body comprising a plurality of first conductors extending in a first direction away from a surface of the substrate and spaced from one another in second and third directions intersecting the first direction and each other, the stacked body having a first region and a second region, a plurality of second conductors extending in the second direction, a plurality of third conductors extending in the third, each third conductor connected to a first end, in the second direction, of a plurality of second conductors in the first region, a plurality of fourth connectors extending in the first direction, each fourth conductor connected to the plurality of second conductors in the second region, and memory cells located between adjacent surfaces of the first and second conductors in the first region.

公开(公告)号：US20180269391A1

公开(公告)日：2018-09-20

申请号：US15704874

申请日：2017-09-14

Applicant: Toshiba Memory Corporation

Inventor： Harumi SEKI ,  Takayuki ISHIKAWA ,  Masumi SAITOH

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L27/2436 ,  H01L45/146

Abstract: According to one embodiment, a memory device includes a first interconnect, a second interconnect, a first layer, a second layer. The first interconnect includes a first region and a second region. The first region extends in a first direction and includes a first metallic element. The second region extends in the first direction and includes the first metallic element and nitrogen. The second interconnect extends in a second direction crossing the first direction. A portion of the second region is positioned between the second interconnect and a portion of the first region. The first layer is provided between the second interconnect and the portion of the second region. The second layer is provided between the first layer and the second interconnect. The second layer includes at least one of silicon or a second oxide. The silicon is monocrystalline, polycrystalline, or amorphous.