公开(公告)号：US20180277192A1

公开(公告)日：2018-09-27

申请号：US15705864

申请日：2017-09-15

Applicant: Toshiba Memory Corporation

Inventor： Chika TANAKA ,  Keiji IKEDA

IPC: G11C11/404 ,  G11C11/4096 ,  G11C11/56 ,  H01L27/12 ,  H01L27/108 ,  G06N3/04

CPC classification number: G11C11/404 ,  G06N3/04 ,  G06N3/049 ,  G06N3/0635 ,  G11C7/1006 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/54 ,  G11C11/565 ,  H01L27/10805 ,  H01L27/1225

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell including a transistor formed of an oxide semiconductor, an insulation film, and a control electrode, and a capacitance element configured to store a charge, the memory cell being configured to store a coupling weight of a neuron model by a charge amount accumulated in the capacitance element; and a control circuit configured to output a signal as a sum of a product between input data of the memory cell and the coupling weight.

公开(公告)号：US20190096481A1

公开(公告)日：2019-03-28

申请号：US15910408

申请日：2018-03-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Chika TANAKA ,  Masumi SAITOH

IPC: G11C13/00 ,  H01L23/528 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/0007 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  G11C2213/79 ,  H01L23/528 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1683

Abstract: A semiconductor memory device includes a substrate, a stacked body comprising a plurality of first conductors extending in a first direction away from a surface of the substrate and spaced from one another in second and third directions intersecting the first direction and each other, the stacked body having a first region and a second region, a plurality of second conductors extending in the second direction, a plurality of third conductors extending in the third, each third conductor connected to a first end, in the second direction, of a plurality of second conductors in the first region, a plurality of fourth connectors extending in the first direction, each fourth conductor connected to the plurality of second conductors in the second region, and memory cells located between adjacent surfaces of the first and second conductors in the first region.

公开(公告)号：US20200242203A1

公开(公告)日：2020-07-30

申请号：US16567923

申请日：2019-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Chika TANAKA ,  Sadayuki Yoshitomi

IPC: G06F17/50

Abstract: According to one embodiment, the computing device includes a modeling processing unit configured to model characteristics of selected cell transistor and to define a non-selected cell transistor as a parasitic resistance component of the selected cell transistor. The computing device further includes a computation processing unit configured to use as a parameter a distance between both ends of an active region of the selected cell transistor, and further to store threshold characteristics of the selected cell transistor present in the memory string as a parameter, and to obtain electrical characteristics of the selected cell transistor. The computing device is used for a circuit simulation of a semiconductor memory device including memory string of a plurality of cell transistors connected to one another in series in a channel direction.

公开(公告)号：US20190295626A1

公开(公告)日：2019-09-26

申请号：US16114178

申请日：2018-08-27

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiji IKEDA ,  Chika TANAKA

IPC: G11C11/4096 ,  H01L27/108 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/56

Abstract: A semiconductor memory device includes a first memory cell that includes a first transistor and a first capacitor, a second transistor having a first terminal that is connected to a first terminal of the first memory cell, a first bit line that is connected to a second terminal of the first memory cell, a second bit line that is connected to a second terminal of the second transistor, and a controller that turns on the first transistor and turns off the second transistor during a write operation on the first memory cell and turns on the first transistor and the second transistor during a read operation on the first memory cell.

公开(公告)号：US20190287617A1

公开(公告)日：2019-09-19

申请号：US16120031

申请日：2018-08-31

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Chika TANAKA ,  Masumi SAITOH

IPC: G11C14/00 ,  H01L27/11502

Abstract: A semiconductor memory includes a first and a second transistor each with one of source/drain connected to a first wiring. The other of the source/drain for each of first and second transistor is connected to the gate of the other transistor. A third and a fourth transistor each have gates connected to a second wiring, one of source/drain of each connected to a third or fifth wiring, the other of the source/drain connected to the other of the source/drain of the first or second transistor. For the third transistor, a gate insulation layer includes a first ferroelectric material. For the fourth transistor, and a gate insulation layer includes a second ferroelectric material.

公开(公告)号：US20180350829A1

公开(公告)日：2018-12-06

申请号：US16041460

申请日：2018-07-20

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tsutomu TEZUKA ,  Fumitaka ARAI ,  Keiji IKEDA ,  Tomomasa UEDA ,  Nobuyoshi SAITO ,  Chika TANAKA ,  Kentaro MIURA ,  Tomoaki SAWABE

IPC: H01L27/11568 ,  G11C16/04 ,  G11C5/06 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11568 ,  G11C5/06 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.

公开(公告)号：US20180331116A1

公开(公告)日：2018-11-15

申请号：US16041577

申请日：2018-07-20

Applicant: Toshiba Memory Corporation

Inventor： Tsutomu TEZUKA ,  Fumitaka ARAI ,  Keiji IKEDA ,  Tomomasa UEDA ,  Nobuyoshi SAITO ,  Chika TANAKA ,  Kentaro MIURA ,  Tomoaki SAWABE

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L27/11565 ,  H01L29/423 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C7/18 ,  G11C8/14

CPC classification number: H01L27/11578 ,  G11C7/18 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/4234

Abstract: According to one embodiment, a memory includes: a first gate of a first transistor and a second gate electrode of the second transistor facing the a semiconductor layer; an oxide semiconductor layer between the first and second transistors and including first to fifth portions in order; a third gate of a first cell facing the first portion; a fourth gate of a third transistor facing the second portion; a fifth gate of a second cell facing the third portion; a sixth gate of a fourth transistor facing the fourth portion; an interconnect connected to the fifth portion; a source line connected to the first transistor; and a bit line connected to the second transistor. A material of the third gate is different from a material of the fourth gate.

公开(公告)号：US20180269257A1

公开(公告)日：2018-09-20

申请号：US15699254

申请日：2017-09-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Chika TANAKA ,  Masumi SAITOH

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

CPC classification number: H01L27/2481 ,  G11C13/0023 ,  G11C13/0038 ,  H01L45/1253

Abstract: This semiconductor memory device includes: global first wiring lines; global second wiring lines; and memory blocks connected to the Global first wiring lines and the global second wiring lines. The memory block includes: local first wiring lines; local second wiring lines; and memory cells connected to the local first wiring lines and the local second wiring lines. The memory cell includes: a variable resistance element; first electrodes disposed on a first surface of the variable resistance element; and second electrodes arranged on a second surface of the variable resistance element. The first electrodes are connected to the local first wiring lines, and the second electrodes are connected to the local second wiring lines.

公开(公告)号：US20180082733A1

公开(公告)日：2018-03-22

申请号：US15445230

申请日：2017-02-28

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Chika TANAKA ,  Keiji Ikeda ,  Toshinori Numata ,  Tsutomu Tezuka

IPC: G11C11/4091 ,  G11C11/404 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C11/404 ,  G11C11/4045 ,  G11C11/4087 ,  G11C11/4094 ,  G11C11/565 ,  H01L27/0688 ,  H01L27/10808 ,  H01L27/10873

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a sense amplifier, a first transfer transistor, a second transfer transistor, and a controller. The memory cell can store a first value and a second value. The sense amplifier amplifies the first value or the second value read from the memory cell to the sense node. The first transfer transistor has a first control terminal connected to the sense node. The second transfer transistor has a second control terminal connected to the sense node. The controller applies a backgate potential to backgate terminals of the first transfer transistor and the second transfer transistor.