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    Three-dimensional memory device and manufacturing method thereof
    12.
    发明授权
    Three-dimensional memory device and manufacturing method thereof 有权

    公开(公告)号：US11538862B2

    公开(公告)日：2022-12-27

    申请号：US17108243

    申请日：2020-12-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-I Wu ,  Yu-Ming Lin

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A three-dimensional memory device includes a stacking structure, memory pillars, and conductive pillars. The stacking structure includes stacking layers stacked along a vertical direction, each stacking layer including a gate layer, a gate dielectric layer, and a channel layer. The gate layer, the gate dielectric layer, and the channel layer extend along a horizontal direction, and the gate dielectric layer is disposed between the gate layer and the channel layer. The memory pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. Each memory pillar comprises a first electrode, a second electrode, and a switching layer between the first and second electrodes. The conductive pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. The memory pillars and the conductive pillars are alternately arranged along the horizontal direction.

    HYBRID MEMORY DEVICE AND METHOD OF FORMING THE SAME
    13.
    发明申请
    HYBRID MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20220231026A1

    公开(公告)日：2022-07-21

    申请号：US17531986

    申请日：2021-11-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-I Wu ,  Yu-Ming Lin

    IPC: H01L27/105

    Abstract: A memory array includes hybrid memory cells, wherein each hybrid memory cell includes a transistor-type memory including a memory film extending on a gate electrode; a channel layer extending on the memory film; a first source/drain electrode extending on the channel layer; and a second source/drain electrode extending along the channel layer; and a resistive-type memory including a resistive memory layer, wherein the resistive memory layer extends between the second source/drain electrode and the channel layer.

    Memory devices and methods of forming the same
    14.
    发明授权
    Memory devices and methods of forming the same 有权

    公开(公告)号：US11309490B2

    公开(公告)日：2022-04-19

    申请号：US16785673

    申请日：2020-02-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-I Wu

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Memory devices and methods of forming the same are provided. A memory device includes a substrate, a first conductive layer, a phase change layer, a selector layer and a second conductive layer. The first conductive layer is disposed over the substrate. The phase change layer is disposed over the first conductive layer. The selector layer is disposed between the phase change layer and the first conductive layer. The second conductive layer is disposed over the phase change layer. In some embodiments, at least one of the phase change layer and the selector layer has a narrow-middle profile.

    Memory Array Including Dummy Regions
    15.
    发明申请
    Memory Array Including Dummy Regions 有权

    公开(公告)号：US20210407569A1

    公开(公告)日：2021-12-30

    申请号：US17064279

    申请日：2020-10-06

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chao-I Wu ,  Sheng-Chen Wang ,  Yu-Ming Lin

    IPC: G11C11/22 ,  H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

    Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.

    Memory device and programming method thereof
    18.
    发明授权
    Memory device and programming method thereof 有权

    公开(公告)号：US12029143B2

    公开(公告)日：2024-07-02

    申请号：US16919071

    申请日：2020-07-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-I Wu

    IPC: H10N70/00 ,  H10N70/20

    CPC classification number: H10N70/8613 ,  H10N70/231 ,  H10N70/8413

    Abstract: A memory device and a programming method of the memory device are provided. The memory device includes a bottom electrode, a heater, a phase change layer and a top electrode. The heater is disposed on the bottom electrode, and includes heat conducting materials different from one another in terms of electrical resistivity. A first one of the heat conducting materials has a periphery wall portion and a bottom plate portion connected to and surrounded by the periphery wall portion. A second one of the heat conducting materials is disposed on the bottom plate portion of the first one of the heat conducting materials, and laterally surrounded by the periphery wall portion of the first one of the heat conducting materials. The phase change layer is disposed on the heater and in contact with the heat conducting materials. The top electrode is disposed on the phase change layer.

    Three-Dimensional Memory Device with Ferroelectric Material
    19.
    发明申请
    Three-Dimensional Memory Device with Ferroelectric Material 有权

    公开(公告)号：US20220359542A1

    公开(公告)日：2022-11-10

    申请号：US17814648

    申请日：2022-07-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chao-I Wu ,  Yu-Ming Lin ,  Han-Jong Chia

    IPC: H01L27/1159 ,  H01L27/11597 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/24

    Abstract: A memory device includes: a first layer stack and a second layer stack formed successively over a substrate, where each of the first and the second layer stacks includes a first metal layer, a second metal layer, and a first dielectric material between the first and the second metal layers; a second dielectric material between the first and the second layer stacks; a gate electrode extending through the first and the second layer stacks, and through the second dielectric material; a ferroelectric material extending along and contacting a sidewall of the gate electrode; and a channel material, where a first portion and a second portion of the channel material extend along and contact a first sidewall of the first layer stack and a second sidewall of the second layer stack, respectively, where the first portion and the second portion of the channel material are separated from each other.

    Memory Array Including Dummy Regions
    20.
    发明申请
    Memory Array Including Dummy Regions 有权

    公开(公告)号：US20220358984A1

    公开(公告)日：2022-11-10

    申请号：US17815032

    申请日：2022-07-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chao-I Wu ,  Sheng-Chen Wang ,  Yu-Ming Lin

    IPC: G11C11/22 ,  H01L27/11597 ,  H01L27/1159 ,  H01L27/11587

    Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.

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