公开(公告)号：US20240357804A1

公开(公告)日：2024-10-24

申请号：US18757580

申请日：2024-06-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： MENG-SHENG CHANG ,  CHIA-EN HUANG ,  YAO-JEN YANG ,  YIH WANG

IPC分类号： H10B20/20 ,  G06F12/14 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H10B99/00

CPC分类号： H10B20/20 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42316 ,  H01L29/7851 ,  H10B99/00 ,  G06F12/1433

摘要： A memory device includes: a substrate; a semiconductor fin over the substrate in a first direction; a first gate electrode and a second gate electrode over the substrate in a second direction, the semiconductor fin extending through the second gate electrode and terminating at the first gate electrode; a first gate dielectric layer arranged between the semiconductor fin and the first gate electrode; and a second gate dielectric layer arranged between the semiconductor fin and the second gate electrode. The second gate electrode is configured as a read transistor of a first memory cell, in which the second gate dielectric layer is kept intact, and the first gate electrode is configured as a program transistor of the first memory cell, in which an occurrence or an absence of an electrical breakdown in the first gate dielectric layer represents a binary logic state of the first memory cell.

公开(公告)号：US12087829B2

公开(公告)日：2024-09-10

申请号：US17500089

申请日：2021-10-13

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Bing Zou ,  Cheng Yeh Hsu

IPC分类号： H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H10B99/00 ,  H01L21/265 ,  H01L21/66

CPC分类号： H01L29/401 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66621 ,  H10B99/00 ,  H01L21/26513 ,  H01L22/12

摘要： Embodiments of the present application provide a semiconductor structure and its fabricating method, and a semiconductor memory. The method of fabricating a semiconductor structure comprises providing a substrate and performing ion implantation on the substrate to form an active area, forming a gate groove on surface of the substrate, measuring depth of the gate groove, and performing ion implantation compensation, if the depth of the gate groove meets a preset condition, on the substrate according to the depth of the gate groove, and forming an ion compensation region in the active area at one side of the gate groove.

公开(公告)号：US12069873B2

公开(公告)日：2024-08-20

申请号：US17462040

申请日：2021-08-31

申请人： eMemory Technology Inc.

发明人： Tsung-Mu Lai ,  Wei-Chen Chang

IPC分类号： H10B99/00 ,  G11C11/416

CPC分类号： H10B99/00 ,  G11C11/416

摘要： A cell array structure includes a first resistive memory cell. The first resistive memory cell includes a well region, a first doped region, a merged region, a first gate structure, a second gate structure and a first metal layer. The first doped region is formed under a surface of the well region. The merged region is formed under the surface of the well region. The first gate structure is formed over the surface of the well region between the first doped region and the merged region. The first gate structure includes a first insulation layer and a first conductive layer. The second gate structure is formed over the merged region. The second gate structure includes a second insulation layer and a second conductive layer. The first metal layer is connected with the first doped region.

公开(公告)号：US12052859B2

公开(公告)日：2024-07-30

申请号：US18066290

申请日：2022-12-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Meng-Sheng Chang ,  Chia-En Huang ,  Yao-Jen Yang ,  Yih Wang

IPC分类号： H10B20/20 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H10B99/00 ,  G06F12/14

CPC分类号： H10B20/20 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42316 ,  H01L29/7851 ,  H10B99/00 ,  G06F12/1433

摘要： A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, a first gate electrode and a second gate electrode over the substrate and extending in a second direction, the semiconductor fin extending through the second gate electrode and terminating on the first gate electrode at one end of the semiconductor fin, and a first gate spacer and a second gate spacer laterally surrounding the first gate electrode and the second gate electrode, respectively. The one end of the semiconductor fin is surrounded by the first gate electrode. The first gate spacer includes a top substantially at a same height of a top of the second gate spacer.

公开(公告)号：US20240237364A1

公开(公告)日：2024-07-11

申请号：US18417830

申请日：2024-01-19

申请人： Micron Technology, Inc.

发明人： Hernan A. Castro ,  Stephen W. Russell ,  Stephen H. Tang

IPC分类号： H10B99/00 ,  G11C8/10 ,  G11C8/12 ,  H01L21/027 ,  H01L21/311 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B53/20 ,  H10B53/40 ,  H10B63/00

CPC分类号： H10B99/00 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/78696 ,  G11C8/10 ,  G11C8/12 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H10B53/20 ,  H10B53/40 ,  H10B63/84

摘要： Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

公开(公告)号：US12029022B2

公开(公告)日：2024-07-02

申请号：US17730561

申请日：2022-04-27

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Fujio Masuoka ,  Nozomu Harada

IPC分类号： H10B99/00 ,  H10B10/00

CPC分类号： H10B10/12 ,  H10B99/00

摘要： A bottom portion of a Ta pillar serving as a contact portion is connected to an N+ layer and a P+ layer, and a gate HfO2 layer is connected to side surfaces of Si pillars and a Ta pillar serving as a contact portion and an upper surface of a SiO2 layer between the Si pillars and the Ta pillar serving as the contact portion. Gate TiN layers are provided on a side surface of the gate HfO2 layer surrounding the Si pillars. Midpoints of the Si pillars and the Ta pillar serving as the contact portion are on one first line in plan view.

公开(公告)号：US12027412B2

公开(公告)日：2024-07-02

申请号：US17814626

申请日：2022-07-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Han-Jong Chia ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC分类号： H01L21/762 ,  G11C7/18 ,  H10B51/20 ,  H10B99/00

CPC分类号： H01L21/76237 ,  G11C7/18 ,  H10B51/20 ,  H10B99/00

摘要： A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric material.

公开(公告)号：US12015089B2

公开(公告)日：2024-06-18

申请号：US17447393

申请日：2021-09-10

申请人： Micron Technology, Inc.

发明人： Witold Kula ,  Gurtej S. Sandhu ,  John A. Smythe

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66 ,  H10B99/00

CPC分类号： H01L29/78642 ,  H01L21/02178 ,  H01L21/02488 ,  H01L21/02568 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78645 ,  H01L29/78696 ,  H10B99/00 ,  H01L21/0262

摘要： A transistor comprising a channel region on a material is disclosed. The channel region comprises a two-dimensional material comprising opposing sidewalls and oriented perpendicular to the material. A gate dielectric is on the two-dimensional material and gates are on the gate dielectric. Semiconductor devices and systems including at least one transistor are disclosed, as well as methods of forming a semiconductor device.

公开(公告)号：US20240185917A1

公开(公告)日：2024-06-06

申请号：US18441881

申请日：2024-02-14

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00 ,  G11C11/402 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/56 ,  G11C13/00 ,  G11C16/04 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H10B12/00 ,  H10B12/10 ,  H10B63/00 ,  H10B99/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： G11C14/0045 ,  G11C11/4026 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0097 ,  G11C14/0018 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/7881 ,  H10B12/10 ,  H10B12/20 ,  H10B63/00 ,  H10B99/00 ,  H10N70/231 ,  H10N70/883 ,  G11C16/0416 ,  G11C2211/4016 ,  G11C2213/76 ,  G11C2213/79 ,  H10N70/8828

摘要： A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

公开(公告)号：US11943938B2

公开(公告)日：2024-03-26

申请号：US17252357

申请日：2020-03-18

申请人： Micron Technology, Inc.

发明人： Paolo Fantini ,  Lorenzo Fratin ,  Paolo Tessariol

IPC分类号： H10B99/00 ,  H01L21/768

CPC分类号： H10B99/00 ,  H01L21/76802 ,  H01L21/76877

摘要： A method for manufacturing a 3D vertical array of memory cells is disclosed. The method comprises:



forming on a substrate a stack of dielectric material layers comprising first and second dielectric material layers alternated to each other;
forming holes through the stack of dielectric material layers, said holes exposing the substrate;
selectively removing the second material layers through said holes to form cavities between adjacent first dielectric material layers;
filling said cavities with a conductive material through said holes to form corresponding conductive material layers;
forming first memory cell access lines from said conductive material layers;
carrying out a conformal deposition of a chalcogenide material through said holes;
forming memory cell storage elements from said deposed chalcogenide material;
filling said holes with conductive material to form corresponding second memory cell access lines.