公开(公告)号：US20230010502A1

公开(公告)日：2023-01-12

申请号：US17370843

申请日：2021-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun CHU ,  Mao-Lin HUANG ,  Chung-Wei HSU ,  Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8234

Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

公开(公告)号：US20220115498A1

公开(公告)日：2022-04-14

申请号：US17070717

申请日：2020-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun CHU ,  Mao-Lin HUANG ,  Chung-Wei HSU ,  Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

公开(公告)号：US20230029370A1

公开(公告)日：2023-01-26

申请号：US17381006

申请日：2021-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin HUANG ,  Lung-Kun CHU ,  Chung-Wei HSU ,  Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A method for processing an integrated circuit includes forming N-type and P-type gate all around transistors and core gate all around transistors. The method deposits a metal gate layer for the P-type transistors. The method forms a passivation layer in-situ with the metal gate layer of the P-type transistor.

公开(公告)号：US20230009349A1

公开(公告)日：2023-01-12

申请号：US17370822

申请日：2021-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Mao-Lin HUANG ,  Lung-Kun CHU ,  Chung-Wei HSU ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/51 ,  H01L21/8234

Abstract: A method for processing an integrated circuit includes forming I/O gate all around transistors and core gate all around transistors. The method performs a regrowth process on an interfacial gate dielectric layer of the I/O gate all around transistors by diffusing metal atoms into the interfacial dielectric layer I/O gate all around transistor. The regrowth process does not diffuse metal atoms into the interfacial gate dielectric layer of the gate all around core transistor.

公开(公告)号：US20220320090A1

公开(公告)日：2022-10-06

申请号：US17476140

申请日：2021-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei HSU ,  Kuo-Cheng CHIANG ,  Mao-Lin HUANG ,  Lung-Kun CHU ,  Jia-Ni YU ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region and second channel nanostructures in a second device region. The first channel nanostructures are disposed between first and second dielectric fins. The second channel nanostructures are disposed between first and third dielectric fins. A gate dielectric layer is formed to surround each of the first and the second channel nanostructures and over the first, the second and the third dielectric fins. A first work function layer is formed to surround each of the first channel nanostructures. A second work function layer is formed to surround each of the second channel nanostructures. A first gap is present between every adjacent first channel nanostructures and a second gap present is between every adjacent second channel nanostructures.

公开(公告)号：US20240282587A1

公开(公告)日：2024-08-22

申请号：US18645181

申请日：2024-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun CHU ,  Jia-Ni YU ,  Chun-Fu LU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L21/477 ,  H01L21/475 ,  H01L21/4757 ,  H01L27/088

CPC classification number: H01L21/477 ,  H01L21/475 ,  H01L21/47573 ,  H01L27/0886

Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.

公开(公告)号：US20240145470A1

公开(公告)日：2024-05-02

申请号：US18406025

申请日：2024-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun CHU ,  Mao-Lin HUANG ,  Chung-Wei HSU ,  Jia-Ni YU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/0883 ,  H01L21/823412 ,  H01L21/823462 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

公开(公告)号：US20240096994A1

公开(公告)日：2024-03-21

申请号：US18167718

申请日：2023-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun CHU ,  Jia-Ni YU ,  Chun-Fu LU ,  Mao-Lin HUANG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A method for forming a semiconductor device is provided. The method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region of a substrate, respectively, and sequentially depositing a gate dielectric layer, an n-type work function metal layer, and a cap layer surrounding each of the first and second channel nanostructures. The cap layer merges in first spaces between adjacent first channel nanostructures and merges in second spaces between adjacent second channel nanostructures. The method further includes selectively removing the cap layer and the n-type work function metal layer in the p-type device region, and depositing a p-type work function metal layer over the cap layer in the n-type device region and the gate dielectric layer in the p-type device region. The p-type work function metal layer merges in the second spaces.

公开(公告)号：US20230360926A1

公开(公告)日：2023-11-09

申请号：US17890980

申请日：2022-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun CHU ,  Jia-Ni YU ,  Chun-Fu LU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L21/477 ,  H01L27/088 ,  H01L21/475 ,  H01L21/4757

CPC classification number: H01L21/477 ,  H01L27/0886 ,  H01L21/475 ,  H01L21/47573

Abstract: A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.