公开(公告)号：US11798899B2

公开(公告)日：2023-10-24

申请号：US17391341

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun-Yu Chen ,  Chun-Lin Tsai ,  Yun-Hsiang Wang ,  Chia-Hsun Wu ,  Jiun-Lei Yu ,  Po-Chih Chen

IPC: H01L23/00 ,  H01L23/58 ,  H01L29/06 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/585 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2225/06541

Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a stacked semiconductor substrate having a semiconductor material disposed over a base semiconductor substrate. The base semiconductor substrate has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench that continuously extends in a closed path between a central region of the stacked semiconductor substrate and a peripheral region of the stacked semiconductor substrate surrounding the central region. The peripheral region of the stacked semiconductor substrate includes a plurality of cracks and the central region is substantially devoid of cracks.

公开(公告)号：US11791388B2

公开(公告)日：2023-10-17

申请号：US16862875

申请日：2020-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Aurelien Gauthier Brun ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Yun-Hsiang Wang

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/778 ,  H01L29/205 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L21/0254 ,  H01L21/32133 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

Abstract: In some embodiments, the present disclosure relates to a transistor device. The transistor device that includes a source contact disposed over a substrate. The source contact has a first side and an opposing second side disposed between a first end and an opposing second end. A drain contact is disposed over the substrate and is separated from the source contact along a first direction. A gate structure is disposed over the substrate between the source contact and the drain contact. The gate structure extends along the first side of the source contact facing the drain contact and also wraps around the first end and the opposing second end of the source contact.

公开(公告)号：US20210242337A1

公开(公告)日：2021-08-05

申请号：US16872551

申请日：2020-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Hsiang Wang ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Chia-Ling Yeh ,  Ching Yu Chen

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

公开(公告)号：US10535730B2

公开(公告)日：2020-01-14

申请号：US15964636

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Karthick Murukesan ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Ker-Hsiao Huo ,  Kuo-Ming Wu ,  Po-Chih Chen ,  Ru-Yi Su ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

公开(公告)号：US20170069617A1

公开(公告)日：2017-03-09

申请号：US15357308

申请日：2016-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： King-Yuen Wong ,  Chun-Wei Hsu ,  Chen-Ju Yu ,  Fu-Wei Yao ,  Jiun-Lei Jerry Yu ,  Fu-Chih Yang ,  Po-Chih Chen

IPC: H01L27/02 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L27/06 ,  H01L21/8258 ,  H01L21/265 ,  H01L29/66 ,  H01L21/306 ,  H01L21/768 ,  H01L23/522 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/26513 ,  H01L21/26546 ,  H01L21/30612 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/8252 ,  H01L21/8258 ,  H01L23/5226 ,  H01L27/0605 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/6609 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/861

Abstract: A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process. The diode is formed proximate to an interface between the silicon substrate and the III-V compound layer. An opening is etched through the III-V compound layer to expose the diode. The opening is filled with a conductive material. Thereby, a via is formed that is coupled to the diode. A High Electron Mobility Transistor (HEMT) device is formed at least partially in the III-V compound layer.

Abstract translation: 提供了其上设置III-V化合物层的硅衬底。 通过离子注入工艺在硅衬底中形成二极管。 二极管形成在硅衬底和III-V化合物层之间的界面附近。 通过III-V化合物层蚀刻开口以暴露二极管。 开口填充有导电材料。 由此，形成与二极管耦合的通孔。 至少部分地在III-V化合物层中形成高电子迁移率晶体管（HEMT）器件。

公开(公告)号：US11715792B2

公开(公告)日：2023-08-01

申请号：US16872551

申请日：2020-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Hsiang Wang ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Chia-Ling Yeh ,  Ching Yu Chen

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

公开(公告)号：US20220375875A1

公开(公告)日：2022-11-24

申请号：US17391341

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun-Yu Chen ,  Chun-Lin Tsai ,  Yun-Hsiang Wang ,  Chia-Hsun Wu ,  Jiun-Lei Yu ,  Po-Chih Chen

IPC: H01L23/00 ,  H01L23/58 ,  H01L25/065 ,  H01L29/06

Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a stacked semiconductor substrate having a semiconductor material disposed over a base semiconductor substrate. The base semiconductor substrate has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench that continuously extends in a closed path between a central region of the stacked semiconductor substrate and a peripheral region of the stacked semiconductor substrate surrounding the central region. The peripheral region of the stacked semiconductor substrate includes a plurality of cracks and the central region is substantially devoid of cracks.