公开(公告)号：US11521915B2

公开(公告)日：2022-12-06

申请号：US16936654

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Hsiang Wang ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.

公开(公告)号：US11798899B2

公开(公告)日：2023-10-24

申请号：US17391341

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun-Yu Chen ,  Chun-Lin Tsai ,  Yun-Hsiang Wang ,  Chia-Hsun Wu ,  Jiun-Lei Yu ,  Po-Chih Chen

IPC: H01L23/00 ,  H01L23/58 ,  H01L29/06 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/585 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2225/06541

Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a stacked semiconductor substrate having a semiconductor material disposed over a base semiconductor substrate. The base semiconductor substrate has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench that continuously extends in a closed path between a central region of the stacked semiconductor substrate and a peripheral region of the stacked semiconductor substrate surrounding the central region. The peripheral region of the stacked semiconductor substrate includes a plurality of cracks and the central region is substantially devoid of cracks.

公开(公告)号：US11791388B2

公开(公告)日：2023-10-17

申请号：US16862875

申请日：2020-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Aurelien Gauthier Brun ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Yun-Hsiang Wang

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/778 ,  H01L29/205 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/41775 ,  H01L21/0254 ,  H01L21/32133 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

Abstract: In some embodiments, the present disclosure relates to a transistor device. The transistor device that includes a source contact disposed over a substrate. The source contact has a first side and an opposing second side disposed between a first end and an opposing second end. A drain contact is disposed over the substrate and is separated from the source contact along a first direction. A gate structure is disposed over the substrate between the source contact and the drain contact. The gate structure extends along the first side of the source contact facing the drain contact and also wraps around the first end and the opposing second end of the source contact.

公开(公告)号：US20210242337A1

公开(公告)日：2021-08-05

申请号：US16872551

申请日：2020-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Hsiang Wang ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Chia-Ling Yeh ,  Ching Yu Chen

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

公开(公告)号：US11664431B2

公开(公告)日：2023-05-30

申请号：US17144671

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Aurelien Gauthier Brun ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Yun-Hsiang Wang

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L29/41758 ,  H01L29/401 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/7786

Abstract: The present disclosure relates to a transistor device. The transistor device includes a plurality of first source/drain contacts disposed over a substrate. A plurality of gate structures are disposed over the substrate between the plurality of first source/drain contacts. The plurality of gate structures wrap around the plurality of first source/drain contacts in a plurality of closed loops. A second source/drain contact is disposed over the substrate between the plurality of gate structures. The second source/drain contact continuously wraps around the plurality of gate structures as a continuous structure.

公开(公告)号：US20210273065A1

公开(公告)日：2021-09-02

申请号：US16862875

申请日：2020-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Aurelien Gauthier Brun ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Yun-Hsiang Wang

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/778 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205

Abstract: In some embodiments, the present disclosure relates to a transistor device. The transistor device that includes a source contact disposed over a substrate. The source contact has a first side and an opposing second side disposed between a first end and an opposing second end. A drain contact is disposed over the substrate and is separated from the source contact along a first direction. A gate structure is disposed over the substrate between the source contact and the drain contact. The gate structure extends along the first side of the source contact facing the drain contact and also wraps around the first end and the opposing second end of the source contact.

公开(公告)号：US20210265241A1

公开(公告)日：2021-08-26

申请号：US16936654

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Hsiang Wang ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.

公开(公告)号：US20220223699A1

公开(公告)日：2022-07-14

申请号：US17144671

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Aurelien Gauthier Brun ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Yun-Hsiang Wang

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/778 ,  H01L29/423

Abstract: The present disclosure relates to a transistor device. The transistor device includes a plurality of first source/drain contacts disposed over a substrate. A plurality of gate structures are disposed over the substrate between the plurality of first source/drain contacts. The plurality of gate structures wrap around the plurality of first source/drain contacts in a plurality of closed loops. A second source/drain contact is disposed over the substrate between the plurality of gate structures. The second source/drain contact continuously wraps around the plurality of gate structures as a continuous structure.

公开(公告)号：US11195945B2

公开(公告)日：2021-12-07

申请号：US16558518

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Cheng Lin ,  Chen-Bau Wu ,  Chun Lin Tsai ,  Haw-Yun Wu ,  Liang-Yu Su ,  Yun-Hsiang Wang

IPC: H01L29/778 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/47 ,  H01L29/417

Abstract: In some embodiments, the present disclosure relates to a high voltage device that includes a substrate comprising a first semiconductor material. A channel layer that comprises a second semiconductor material is arranged over the substrate. An active layer that comprises a third semiconductor material is arranged over the channel layer. Over the active layer is a source contact spaced apart from a drain contact. A gate structure is arranged laterally between the source and drain contacts and over the active layer to define a high electron mobility transistor (HEMT) device. Between the gate structure and the source contact is a cap structure, which is coupled to the source contact and laterally spaced from the gate structure. The cap structure and a gate electrode of the gate structure comprise a same material.

公开(公告)号：US11715792B2

公开(公告)日：2023-08-01

申请号：US16872551

申请日：2020-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Hsiang Wang ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Chia-Ling Yeh ,  Ching Yu Chen

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.