公开(公告)号：US20240141553A1

公开(公告)日：2024-05-02

申请号：US18191129

申请日：2023-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pu-Fang CHEN ,  Ching Yu Chen

IPC: C30B29/06 ,  C30B15/20 ,  C30B33/02 ,  H01L21/02

CPC classification number: C30B29/06 ,  C30B15/203 ,  C30B15/206 ,  C30B33/02 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/02598

Abstract: A manufacturing process is described to evaluate and select raw semiconductor wafers in preparation for epitaxial layer formation. The manufacturing process first produces a single crystal ingot during which a seed pulling velocity and temperature gradient are closely controlled. The resulting ingot is vacancy-rich with relatively few self-interstitial defects. Selected wafers can advance to a high-temperature nitridation annealing operation that further reduces the number of interstitials while increasing the vacancies. Substrates characterized by a high vacancy density can then be used to optimize an epitaxial layer deposition process.

公开(公告)号：US11715792B2

公开(公告)日：2023-08-01

申请号：US16872551

申请日：2020-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Hsiang Wang ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Chia-Ling Yeh ,  Ching Yu Chen

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

公开(公告)号：US11522067B2

公开(公告)日：2022-12-06

申请号：US17225482

申请日：2021-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Yeh ,  Ching Yu Chen

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L21/768 ,  H01L23/31 ,  H01L21/02 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) device and a method of forming the same are provided. The method includes forming a first III-V compound layer over a substrate. A second III-V compound layer is formed over the first III-V compound layer. The second III-V compound layer has a greater band gap than the first III-V compound layer. A third III-V compound layer is formed over the second III-V compound layer. The third III-V compound layer and the first III-V compound layer comprise a same III-V compound. A passivation layer is formed along a topmost surface and sidewalls of the third III-V compound layer. A fourth III-V compound layer is formed over the second III-V compound layer. The fourth III-V compound layer has a greater band gap than the first III-V compound layer.

公开(公告)号：US20210242337A1

公开(公告)日：2021-08-05

申请号：US16872551

申请日：2020-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Hsiang Wang ,  Chun Lin Tsai ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Chia-Ling Yeh ,  Ching Yu Chen

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

公开(公告)号：US20210226040A1

公开(公告)日：2021-07-22

申请号：US17225482

申请日：2021-04-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Yeh ,  Ching Yu Chen

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L21/768 ,  H01L23/31 ,  H01L21/02 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) device and a method of forming the same are provided. The method includes forming a first III-V compound layer over a substrate. A second III-V compound layer is formed over the first III-V compound layer. The second III-V compound layer has a greater band gap than the first III-V compound layer. A third III-V compound layer is formed over the second III-V compound layer. The third III-V compound layer and the first III-V compound layer comprise a same III-V compound. A passivation layer is formed along a topmost surface and sidewalls of the third III-V compound layer. A fourth III-V compound layer is formed over the second III-V compound layer. The fourth III-V compound layer has a greater band gap than the first III-V compound layer.