公开(公告)号：US20210074913A1

公开(公告)日：2021-03-11

申请号：US16950753

申请日：2020-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung-Ying LEE ,  Shao-Ming YU ,  Yu-Chao LIN

IPC: H01L45/00

Abstract: A phase change memory device includes a bottom electrode, a bottom memory layer, a top memory layer, and a top electrode. The bottom memory layer is over the bottom electrode. The bottom memory layer has a first height and includes a tapered portion and a neck portion. The tapered portion has a second height. A ratio of the second height to the first height is in a range of about 0.2 to about 0.5. The neck portion is between the tapered portion and the bottom electrode. The top memory layer is over the bottom memory layer. The tapered portion of the bottom memory layer tapers in a direction from the top memory layer toward the neck portion. The top electrode is over the top memory layer.

公开(公告)号：US20220310919A1

公开(公告)日：2022-09-29

申请号：US17839322

申请日：2022-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chao LIN ,  Yuan-Tien TU ,  Shao-Ming YU ,  Tung-Ying LEE

IPC: H01L45/00

Abstract: A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer. The memory cell includes a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the phase change element. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating.

公开(公告)号：US20210020763A1

公开(公告)日：2021-01-21

申请号：US17065235

申请日：2020-10-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Sheng YUN ,  Shao-Ming YU ,  Tung-Ying LEE ,  Chih-Chieh YEH

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A device includes a semiconductor fin, a first epitaxy structure and a gate stack. The semiconductor fin protrudes from a substrate. The first epitaxy feature laterally surrounds a first portion of the semiconductor fin. The gate stack laterally surrounds a second portion of the semiconductor fin above the first portion of the semiconductor fin, wherein the second portion of the semiconductor fin has a lower surface roughness than the first epitaxy feature.

公开(公告)号：US20200286857A1

公开(公告)日：2020-09-10

申请号：US16881675

申请日：2020-05-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Sheng YUN ,  Shao-Ming YU ,  Chih-Chieh YEH

IPC: H01L25/04 ,  H01L21/70 ,  H01L21/027 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A method includes forming a fin structure over a semiconductor substrate; forming a liner covering the fin structure; etching back the liner to expose an upper portion of the fin structure; forming a spacer covering the upper portion of the fin structure; etching the liner to expose a middle portion of the fin structure, wherein the remaining liner covers a lower portion of the fin structure; etching the middle portion of the fin structure; and forming a first source/drain structure surrounding the middle portion of the fin structure.

公开(公告)号：US20200152870A1

公开(公告)日：2020-05-14

申请号：US16509105

申请日：2019-07-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chao LIN ,  Yuan-Tien TU ,  Shao-Ming YU ,  Tung-Ying LEE

IPC: H01L45/00

Abstract: A method of forming a phase change random access memory (PCRAM) device includes forming a phase change element over a bottom electrode and a top electrode over the phase change element, forming a protection layer around the phase change element, and forming a nitrogen-containing sidewall spacer layer around the protection layer after forming the protection layer.

公开(公告)号：US20190123163A1

公开(公告)日：2019-04-25

申请号：US16198046

申请日：2018-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Lin YANG ,  Tung Ying LEE ,  Shao-Ming YU ,  Chao-Ching CHENG ,  Tzu-Chiang CHEN ,  Chao-Hsien HUANG

IPC: H01L29/49 ,  H01L29/06 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/764 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.

公开(公告)号：US20180342480A1

公开(公告)日：2018-11-29

申请号：US15795191

申请日：2017-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Sheng YUN ,  Shao-Ming YU ,  Chih-Chieh YEH

IPC: H01L25/04 ,  H01L21/027 ,  H01L21/70

Abstract: A vertical transistor device and its fabrication method are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and a fin portion. The fin portion is located on the bottom portion. The fin portion includes an upper portion and a lower portion located between the bottom portion of the semiconductor substrate and the upper portion. The lower portion includes a narrow portion having a width smaller than a width of the upper portion, and the narrow portion contacts an interface portion of the upper portion. The sources/drains are disposed on the on the narrow portion of the lower portion of the fin portion. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the narrow portions where the sources are disposed.

公开(公告)号：US20200052086A1

公开(公告)日：2020-02-13

申请号：US16657873

申请日：2019-10-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Lin YANG ,  Tung Ying LEE ,  Shao-Ming YU ,  Chao-Ching CHENG ,  Tzu-Chiang CHEN ,  Chao-Hsien HUANG

IPC: H01L29/49 ,  H01L21/02 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/764 ,  H01L21/311 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.

公开(公告)号：US20190019888A1

公开(公告)日：2019-01-17

申请号：US15649724

申请日：2017-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Sheng YUN ,  Shao-Ming YU ,  Chih-Chieh YEH

IPC: H01L29/78 ,  H01L27/105 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234

Abstract: A vertical transistor device and a method for fabricating the same are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and fin portions located on the bottom portion. Each of the fin portions includes an upper portion and a lower portion. The lower portion is located between the bottom portion of the semiconductor substrate and the upper portion, in which the lower portion includes recesses. The first sources/drains are disposed on terminals of the upper portions of the fin portions. The second sources/drains are disposed on the recesses of the lower portions of the fin portions, in which the sources/drains are not merged with each other. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the recesses on the lower portions of the fin portions.

公开(公告)号：US20180277658A1

公开(公告)日：2018-09-27

申请号：US15631012

申请日：2017-06-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Sheng YUN ,  Shao-Ming YU ,  Tung-Ying LEE ,  Chih-Chieh YEH

IPC: H01L29/66 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device is provided by follows. A fin is formed over a substrate. A spacer is formed on a sidewall of a first portion of the fin. An epitaxy feature is grown from a second portion of the fin that is in a position lower than the first portion of the fin, in which the forming the epitaxy feature is performed after the forming the spacer. The spacer is removed to expose the first portion of the fin. A gate stack is formed around the exposed first portion of the fin.