公开(公告)号：US20210057539A1

公开(公告)日：2021-02-25

申请号：US17080575

申请日：2020-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHIANG ,  Chen-Feng HSU ,  Chao-Ching CHENG ,  Tzu-Chiang CHEN ,  Tung Ying LEE ,  Wei-Sheng YUN ,  Yu-Lin YANG

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3105

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

公开(公告)号：US20190123163A1

公开(公告)日：2019-04-25

申请号：US16198046

申请日：2018-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Lin YANG ,  Tung Ying LEE ,  Shao-Ming YU ,  Chao-Ching CHENG ,  Tzu-Chiang CHEN ,  Chao-Hsien HUANG

IPC: H01L29/49 ,  H01L29/06 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/764 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.

公开(公告)号：US20180263684A1

公开(公告)日：2018-09-20

申请号：US15988624

申请日：2018-05-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying LEE ,  Ziwei FANG ,  Yee-Chia YEO ,  Meng-Hsuan HSIAO

IPC: A61B18/14 ,  A61B18/00

CPC classification number: A61B18/1445 ,  A61B17/285 ,  A61B17/29 ,  A61B17/295 ,  A61B2017/2825 ,  A61B2017/2926 ,  A61B2018/00184 ,  A61B2018/00589 ,  A61B2018/00601 ,  A61B2018/0063 ,  A61B2018/1455 ,  A61B2018/1465 ,  A61B2090/034

Abstract: In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

公开(公告)号：US20180151564A1

公开(公告)日：2018-05-31

申请号：US15429844

申请日：2017-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying LEE ,  Chih Chieh YEH ,  Tsung-Lin LEE ,  Yee-Chia YEO ,  Meng-Hsuan HSIAO

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming openings adjacent to the patterned sacrificial layer and source/drain structure. A dielectric layer is formed in the openings. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source/drain structure. A conductive layer is formed in the contact opening.

公开(公告)号：US20210217665A1

公开(公告)日：2021-07-15

申请号：US17141126

申请日：2021-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying LEE ,  Tzu-Chung WANG ,  Kai-Tai CHANG ,  Wei-Sheng YUN

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/04 ,  H01L29/78

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a plurality of fins on a substrate. A fin end spacer is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. A gate electrode layer is formed on the insulating layer and wrapping around the each channel region. Sidewall spacers are formed on the gate electrode layer.

公开(公告)号：US20190131431A1

公开(公告)日：2019-05-02

申请号：US15798270

申请日：2017-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching CHENG ,  Chen-Feng HSU ,  Tzu-Chiang CHEN ,  Tung Ying LEE ,  Wei-Sheng YUN ,  Yu-Lin YANG

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

公开(公告)号：US20180166327A1

公开(公告)日：2018-06-14

申请号：US15620063

申请日：2017-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hsuan HSIAO ,  Yee-Chia YEO ,  Tung Ying LEE ,  Chih Chieh YEH

IPC: H01L21/768 ,  H01L27/088 ,  H01L21/28

CPC classification number: H01L21/76802 ,  H01L21/28008 ,  H01L21/76831 ,  H01L21/76877 ,  H01L27/0886 ,  H01L27/10879 ,  H01L29/41791 ,  H01L2029/7858

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

公开(公告)号：US20180151565A1

公开(公告)日：2018-05-31

申请号：US15602807

申请日：2017-05-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying LEE ,  Ziwei FANG ,  Yee-Chia YEO ,  Meng-Hsuan HSIAO

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L21/02 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

公开(公告)号：US20200227534A1

公开(公告)日：2020-07-16

申请号：US16837853

申请日：2020-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHIANG ,  Chen-Feng HSU ,  Chao-Ching CHENG ,  Tzu-Chiang CHEN ,  Tung Ying LEE ,  Wei-Sheng YUN ,  Yu-Lin YANG

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/78

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

公开(公告)号：US20200098876A1

公开(公告)日：2020-03-26

申请号：US16426428

申请日：2019-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying LEE ,  Tzu-Chung WANG ,  Kai-Tai CHANG ,  Wei-Sheng YUN

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04 ,  H01L21/02 ,  H01L21/8234

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a plurality of fins on a substrate. A fin end spacer is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. A gate electrode layer is formed on the insulating layer and wrapping around the each channel region. Sidewall spacers are formed on the gate electrode layer.