公开(公告)号：US20200328123A1

公开(公告)日：2020-10-15

申请号：US16911665

申请日：2020-06-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsiao-Han LIU ,  Chih-Hao WANG ,  Kuo-Cheng CHIANG ,  Shi-Ning JU ,  Kuan-Lun CHENG

IPC: H01L21/8234 ,  H01L27/088

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure formed over a substrate. The semiconductor structure further includes first nanostructures, second nanostructures, third nanostructures, and fourth nanostructures. The semiconductor structure further includes a first gate structure wrapping around the first nanostructures and the second nanostructures, and a second gate structure wrapping around the third nanostructures and the fourth nanostructures. In addition, a first lateral distance between the first fin structure and the second fin structure is shorter than a second lateral distance between the third fin structure and the fourth fin structure, and the first fin structure and the second fin structure are narrower than the third fin structure and the fourth fin structure.

公开(公告)号：US20200258999A1

公开(公告)日：2020-08-13

申请号：US16858891

申请日：2020-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/311

Abstract: Structures and formation methods of a semiconductor device structure are provided. The formation method includes forming a fin structure over a semiconductor substrate and forming a first isolation feature in the fin structure. The formation method also includes forming a second isolation feature over the semiconductor substrate after the formation of the first isolation feature. The fin structure and the first isolation feature protrude from the second isolation feature. The formation method further includes forming gate stacks over the second isolation feature, wherein the gate stacks surround the fin structure and the first isolation feature.

公开(公告)号：US20200243665A1

公开(公告)日：2020-07-30

申请号：US16260483

申请日：2019-01-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Zhi-Chang LIN ,  Kuan-Ting PAN ,  Chih-Hao WANG ,  Shi-Ning JU

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/033 ,  H01L27/088

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure extending above an isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and the top surface of the capping layer is higher than the top surface of the first fin structure and the top surface of the second fin structure. The semiconductor device structure includes a first gate structure formed over first fin structure, and a second gate structure formed over the second fin structure. The first gate structure and the second gate structure are separated by the dummy fin structure and the capping layer.

公开(公告)号：US20200127124A1

公开(公告)日：2020-04-23

申请号：US16226827

申请日：2018-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Ting PAN ,  Shi-Ning JU ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: A method for forming a FinFET device structure includes forming a first fin structure in a core region of a substrate and a second fin structure in an input/output region of the substrate with a fin top layer and a hard mask layer over the fin structures. The method also includes forming a dummy oxide layer across the fin structures. The method also includes forming a dummy gate structure over the dummy oxide layer. The method also includes removing the dummy gate structure over fin structures. The method also includes removing the dummy oxide layer and trimming the fin structures. The method also includes forming first and second oxide layers across the first and second fin structures. The method also includes forming first and second gate structures over the first and second oxide layers across the first and second fin structures.

公开(公告)号：US20230014998A1

公开(公告)日：2023-01-19

申请号：US17379936

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Kuan-Lun CHENG ,  Guan-Lin CHEN ,  Kuan-Ting PAN

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.

公开(公告)号：US20220344333A1

公开(公告)日：2022-10-27

申请号：US17476418

申请日：2021-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei Jhan ,  Kuan-Ting Pan ,  Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, an isolation feature embedded in the substrate and laterally between the first and second semiconductor channels, a first liner layer laterally surrounding the isolation feature between the isolation feature and the first semiconductor channel, and a second liner layer laterally surrounding the first liner layer between the first liner layer and the first semiconductor channel.

公开(公告)号：US20220093595A1

公开(公告)日：2022-03-24

申请号：US17027322

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Ting PAN ,  Kuo-Cheng CHIANG ,  Shi-Ning JU ,  Yi-Ruei JHAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material.

公开(公告)号：US20210159311A1

公开(公告)日：2021-05-27

申请号：US16697647

申请日：2019-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ting LAN ,  Guan-Lin CHEN ,  Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: Semiconductor structures and method for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a first fin structure including first semiconductor material layers and second semiconductor material layers alternately stacked over a substrate and forming an isolation structure surrounding the first fin structure. The method for manufacturing the semiconductor structure also includes forming a first capping layer over the isolation structure and covering a top surface and sidewalls of the first fin structure and etching the isolation structure to form a first gap between the first capping layer and a top surface of the isolation structure. The method for manufacturing the semiconductor structure also includes forming a protection layer covering a sidewall of the first capping layer and filling in the first gap.

公开(公告)号：US20200321453A1

公开(公告)日：2020-10-08

申请号：US16910450

申请日：2020-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Ting PAN ,  Shi-Ning JU ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762

Abstract: A fin field effect transistor device structure includes a first fin structure formed over a substrate. The structure also includes a fin top layer formed over a top portion of the first fin structure. The structure also includes a first oxide layer formed across the first fin structure and the fin top layer. The structure also includes a first gate structure formed over the first oxide layer across the first fin structure.

公开(公告)号：US20200091142A1

公开(公告)日：2020-03-19

申请号：US16133795

申请日：2018-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Ting PAN ,  Shi-Ning JU ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/308 ,  H01L21/8234

Abstract: A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.