公开(公告)号：US20220139828A1

公开(公告)日：2022-05-05

申请号：US17648138

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-En Lee ,  Po-Yu Huang ,  Shih-Che Lin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02 ,  H01L21/768 ,  H01L21/3115

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity β-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity β-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity β-W phase. The β-W converts to a low-resistivity α-phase of tungsten in the regions not pre-treated with impurities.

公开(公告)号：US20210091190A1

公开(公告)日：2021-03-25

申请号：US16899140

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yu Huang ,  Shih-Che Lin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/66 ,  H01L21/285

Abstract: A source/drain is disposed over a substrate. A source/drain contact is disposed over the source/drain. A first via is disposed over the source/drain contact. The first via has a laterally-protruding bottom portion and a top portion that is disposed over the laterally-protruding bottom portion.

公开(公告)号：US12142565B2

公开(公告)日：2024-11-12

申请号：US17874804

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Che Lin ,  Po-Yu Huang ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Rueijer Lin ,  Wei-Jung Lin ,  Chen-Yuan Kao

IPC: H01L23/535 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/48 ,  H01L29/45

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

公开(公告)号：US20230343712A1

公开(公告)日：2023-10-26

申请号：US18345388

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Che Lin ,  Po-Yu Huang ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Rueijer Lin ,  Wei-Jung Lin ,  Chen-Yuan Kao

IPC: H01L23/535 ,  H01L21/311 ,  H01L21/768 ,  H01L21/285 ,  H01L23/48 ,  H01L29/45 ,  H01L21/3213

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/32134 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/481 ,  H01L29/45

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

公开(公告)号：US20220359675A1

公开(公告)日：2022-11-10

申请号：US17872160

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yu Huang ,  Shih-Che Lin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/66 ,  H01L29/08

Abstract: A source/drain is disposed over a substrate. A source/drain contact is disposed over the source/drain. A first via is disposed over the source/drain contact. The first via has a laterally-protruding bottom portion and a top portion that is disposed over the laterally-protruding bottom portion.

公开(公告)号：US11177212B2

公开(公告)日：2021-11-16

申请号：US16846910

申请日：2020-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yu Huang ,  Shih-Che Lin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC: H01L21/768 ,  H01L23/522 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L23/528

Abstract: A method and structure for forming semiconductor device includes forming a contact via opening in a first dielectric layer, where the contact via opening exposes a first portion of a contact etch stop layer (CESL). The method further includes etching both the first portion of the CESL exposed by the contact via opening and adjacent lateral portions of the CESL to expose a source/drain contact and form an enlarged contact via opening having cavities disposed on either side of a bottom portion of the enlarged contact via opening. The method further includes forming a passivation layer on sidewall surfaces of the enlarged contact via opening including on sidewall surfaces of the cavities. The method further includes depositing a first metal layer within the enlarged contact via opening and within the cavities to provide a contact via in contact with the exposed source/drain contact.

公开(公告)号：US20210098376A1

公开(公告)日：2021-04-01

申请号：US16984884

申请日：2020-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Che Lin ,  Po-Yu Huang ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Rueijer Lin ,  Wei-Jung Lin ,  Chen-Yuan Kao

IPC: H01L23/535 ,  H01L29/45 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/768

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.