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公开(公告)号:US12057392B2
公开(公告)日:2024-08-06
申请号:US17648138
申请日:2022-01-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jia-En Lee , Po-Yu Huang , Shih-Che Lin , Chao-Hsun Wang , Kuo-Yi Chao , Mei-Yun Wang , Feng-Yu Chang
IPC: H01L23/522 , H01L21/3115 , H01L21/768 , H01L23/528 , H01L23/532 , H01L49/02
CPC classification number: H01L23/5228 , H01L21/31155 , H01L21/76802 , H01L21/76825 , H01L21/76877 , H01L23/528 , H01L23/53257 , H01L28/24
Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity β-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity β-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity β-W phase. The β-W converts to a low-resistivity α-phase of tungsten in the regions not pre-treated with impurities.
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公开(公告)号:US11532561B2
公开(公告)日:2022-12-20
申请号:US16984884
申请日:2020-08-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Che Lin , Po-Yu Huang , Chao-Hsun Wang , Kuo-Yi Chao , Mei-Yun Wang , Feng-Yu Chang , Rueijer Lin , Wei-Jung Lin , Chen-Yuan Kao
IPC: H01L23/535 , H01L29/45 , H01L21/311 , H01L21/3213 , H01L21/768 , H01L21/285 , H01L23/48
Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.
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公开(公告)号:US10923573B2
公开(公告)日:2021-02-16
申请号:US16572084
申请日:2019-09-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chao-Hsun Wang , Yu-Feng Yin , Kuo-Yi Chao , Mei-Yun Wang , Feng-Yu Chang , Chen-Yuan Kao
IPC: H01L29/00 , H01L31/036 , H01L29/423 , H01L29/45 , H01L21/28 , H01L29/49 , H01L29/78 , H01L29/66
Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.
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公开(公告)号:US10418453B2
公开(公告)日:2019-09-17
申请号:US15883238
申请日:2018-01-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chao-Hsun Wang , Yu-Feng Yin , Kuo-Yi Chao , Mei-Yun Wang , Feng-Yu Chang , Chen-Yuan Kao
IPC: H01L29/00 , H01L31/036 , H01L29/423 , H01L29/45 , H01L21/28 , H01L29/66 , H01L29/78 , H01L29/49
Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.
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公开(公告)号:US12278188B2
公开(公告)日:2025-04-15
申请号:US18345388
申请日:2023-06-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Che Lin , Po-Yu Huang , Chao-Hsun Wang , Kuo-Yi Chao , Mei-Yun Wang , Feng-Yu Chang , Rueijer Lin , Wei-Jung Lin , Chen-Yuan Kao
IPC: H01L23/535 , H01L21/285 , H01L21/311 , H01L21/3213 , H01L21/768 , H01L23/48 , H01L29/45
Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.
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公开(公告)号:US20240379378A1
公开(公告)日:2024-11-14
申请号:US18781018
申请日:2024-07-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Pang-Sheng Chang , Yu-Feng Yin , Chao-Hsun Wang , Kuo-Yi Chao , Fu-Kai Yang , Mei-Yun Wang , Feng-Yu Chang , Chen-Yuan Kao , Chia-Yang Hung , Chia-Sheng Chang , Shu-Huei Suen , Jyu-Horng Shieh , Sheng-Liang Pan , Jack Kuo-Ping Kuo , Shao-Jyun Wu
IPC: H01L21/321 , H01L21/28 , H01L29/49 , H01L29/66 , H01L29/78
Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, a conductive layer disposed on the gate electrode, and a gate contact disposed on the conductive layer. The conductive layer extends from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure. The gate electrode includes at least a first metal, and the conductive layer includes at least the first metal and a second metal different from the first metal. Laterally the conductive layer is fully between opposing sidewalls of the metal gate structure.
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公开(公告)号:US12142565B2
公开(公告)日:2024-11-12
申请号:US17874804
申请日:2022-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Che Lin , Po-Yu Huang , Chao-Hsun Wang , Kuo-Yi Chao , Mei-Yun Wang , Feng-Yu Chang , Rueijer Lin , Wei-Jung Lin , Chen-Yuan Kao
IPC: H01L23/535 , H01L21/285 , H01L21/311 , H01L21/3213 , H01L21/768 , H01L23/48 , H01L29/45
Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.
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公开(公告)号:US20230343712A1
公开(公告)日:2023-10-26
申请号:US18345388
申请日:2023-06-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Che Lin , Po-Yu Huang , Chao-Hsun Wang , Kuo-Yi Chao , Mei-Yun Wang , Feng-Yu Chang , Rueijer Lin , Wei-Jung Lin , Chen-Yuan Kao
IPC: H01L23/535 , H01L21/311 , H01L21/768 , H01L21/285 , H01L23/48 , H01L29/45 , H01L21/3213
CPC classification number: H01L23/535 , H01L21/28518 , H01L21/31116 , H01L21/32134 , H01L21/76805 , H01L21/7684 , H01L21/76843 , H01L21/76895 , H01L23/481 , H01L29/45
Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.
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公开(公告)号:US20210098376A1
公开(公告)日:2021-04-01
申请号:US16984884
申请日:2020-08-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Che Lin , Po-Yu Huang , Chao-Hsun Wang , Kuo-Yi Chao , Mei-Yun Wang , Feng-Yu Chang , Rueijer Lin , Wei-Jung Lin , Chen-Yuan Kao
IPC: H01L23/535 , H01L29/45 , H01L21/311 , H01L21/3213 , H01L21/285 , H01L21/768
Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.
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公开(公告)号:US20240355740A1
公开(公告)日:2024-10-24
申请号:US18345303
申请日:2023-06-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Feng-Yu Chang , Sheng-Hsuan Lin , Shu-Lan Chang , Kai-Yi Chu , Meng-Hsien Lin , Pei-Hsuan Lee , Pei Shan Chang , Chih-Chien Chi , Chun-I Tsai , Wei-Jung Lin , Chih-Wei Chang , Ming-Hsing Tsai , Syun-Ming Jang , Wei-Jen Lo
IPC: H01L23/532 , H01L21/768 , H01L21/8234 , H01L27/088 , H01L29/417 , H01L29/66 , H01L29/78
CPC classification number: H01L23/53266 , H01L21/7684 , H01L21/76876 , H01L21/76877 , H01L21/76897 , H01L21/823431 , H01L27/0886 , H01L29/41791 , H01L29/66795 , H01L29/785
Abstract: A method includes forming a dielectric layer over a conductive feature, and etching the dielectric layer to form an opening. The conductive feature is exposed through the opening. The method further includes forming a tungsten liner in the opening, wherein the tungsten liner contacts sidewalls of the dielectric layer, depositing a tungsten layer to fill the opening, and planarizing the tungsten layer. Portions of the tungsten layer and the tungsten liner in the opening form a contact plug.
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