中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.016 seconds)

    Method with CMP for metal ion prevention
    11.
    发明授权
    Method with CMP for metal ion prevention 有权

    公开(公告)号：US11211256B2

    公开(公告)日：2021-12-28

    申请号：US16801526

    申请日：2020-02-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

    IPC: H01L21/321 ,  H01L21/768 ,  H01L21/02 ,  H01L21/67 ,  C09G1/02 ,  H01L21/3213

    Abstract: The present disclosure provides a method for fabricating a semiconductor structure that includes a first dielectric layer over a semiconductor substrate, and a first cap layer over the first dielectric layer. The method includes forming a first metal feature in the first dielectric layer; performing a first CMP process on the first metal feature using a first rotation rate; and performing a second CMP process on the first metal feature using a second rotation rate slower than the first rotation rate. The second CMP process may be time-based. The second CMP process may stop on the first cap layer. After performing the second CMP process, the method includes removing the first cap layer. The first CMP process may have a first polishing rate to the first metal feature. The second CMP process may have a second polishing rate to the first metal feature lower than the first polishing rate.

    Methods of performing chemical-mechanical polishing process in semiconductor devices
    12.
    发明授权
    Methods of performing chemical-mechanical polishing process in semiconductor devices 有权

    公开(公告)号：US11152255B2

    公开(公告)日：2021-10-19

    申请号：US16712430

    申请日：2019-12-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

    IPC: H01L21/768 ,  H01L21/321 ,  H01L23/535 ,  H01L23/532

    Abstract: A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.

    Semiconductor device and manufacturing method thereof
    14.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US11127680B2

    公开(公告)日：2021-09-21

    申请号：US15632184

    申请日：2017-06-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Shih-Kang Fu ,  Hsien-Chang Wu ,  Li-Lin Su ,  Ming-Han Lee ,  Shau-Lin Shue

    IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528

    Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.

    Method with CMP for Metal Ion Prevention
    17.
    发明申请
    Method with CMP for Metal Ion Prevention 有权

    公开(公告)号：US20210265172A1

    公开(公告)日：2021-08-26

    申请号：US16801526

    申请日：2020-02-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

    IPC: H01L21/321 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3213 ,  C09G1/02 ,  H01L21/67

    Abstract: The present disclosure provides a method for fabricating a semiconductor structure that includes a first dielectric layer over a semiconductor substrate, and a first cap layer over the first dielectric layer. The method includes forming a first metal feature in the first dielectric layer; performing a first CMP process on the first metal feature using a first rotation rate; and performing a second CMP process on the first metal feature using a second rotation rate slower than the first rotation rate. The second CMP process may be time-based. The second CMP process may stop on the first cap layer. After performing the second CMP process, the method includes removing the first cap layer. The first CMP process may have a first polishing rate to the first metal feature. The second CMP process may have a second polishing rate to the first metal feature lower than the first polishing rate.

    Methods of Performing Chemical-Mechanical Polishing Process in Semiconductor Devices
    18.
    发明申请
    Methods of Performing Chemical-Mechanical Polishing Process in Semiconductor Devices 审中-公开

    公开(公告)号：US20200312708A1

    公开(公告)日：2020-10-01

    申请号：US16712430

    申请日：2019-12-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Kang Fu ,  Ming-Han Lee ,  Shau-Lin Shue

    IPC: H01L21/768 ,  H01L21/321 ,  H01L23/532 ,  H01L23/535

    Abstract: A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.

    Method for forming conductive structure using polishing process
    19.
    发明授权
    Method for forming conductive structure using polishing process 有权

    公开(公告)号：US10163700B2

    公开(公告)日：2018-12-25

    申请号：US14989036

    申请日：2016-01-06

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Kang Fu ,  Ming-Han Lee

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/321

    Abstract: Semiconductor structures and methods for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a sacrificial layer over the dielectric layer. The method for manufacturing a semiconductor structure further includes forming a trench through the sacrificial layer and the dielectric layer and forming a conductive structure in the trench. The method for manufacturing a semiconductor structure further includes removing the sacrificial layer. In addition, a top surface of the conductive feature is not level with a top surface of the dielectric layer after the sacrificial layer is removed.

Patent Agency Ranking