-
公开(公告)号：US20200006542A1
公开(公告)日：2020-01-02
申请号：US16194140
申请日：2018-11-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Timothy Vasen , Gerben Doornbos , Matthias Passlack
IPC: H01L29/775 , H01L29/205 , H01L29/08 , H01L29/10 , H01L29/66
Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.
-
公开(公告)号：US12089423B2
公开(公告)日：2024-09-10
申请号：US18311839
申请日：2023-05-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Marcus Johannes Henricus Van Dal , Timothy Vasen , Gerben Doornbos
CPC classification number: H10K10/484 , H10K10/491 , H10K19/10 , H10K85/221
Abstract: The current disclosure describes techniques for forming semiconductor structures having multiple semiconductor strips configured as channel portions. In the semiconductor structures, diffusion break structures are formed after the gate structures are formed so that the structural integrity of the semiconductor strips adjacent to the diffusion break structures will not be compromised by a subsequent gate formation process. The diffusion break extends downward from an upper surface until all the semiconductor strips of the adjacent channel portions are truncated by the diffusion break.
-
公开(公告)号：US11557726B2
公开(公告)日：2023-01-17
申请号：US17068736
申请日：2020-10-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
IPC: H01L21/00 , H01L51/00 , C23C16/455 , C23C16/56 , H01L23/544 , H01L51/05
Abstract: Provided herein are wafers that can be used to align carbon nanotubes, as well as methods of making and using the same. Such wafers include alignment areas that have four sides and a surface charge, where the alignment areas are surrounded by areas that have a surface charge of a different polarity. Methods of the disclosure may include depositing and selectively etching a number of hardmasks on a substrate. The described methods may also include depositing a carbon nanotube on such a wafer.
-
14.发明授权公开(公告)号：US11437594B2
公开(公告)日：2022-09-06
申请号：US16940321
申请日：2020-07-27
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Timothy Vasen , Mark Van Dal , Gerben Doornbos , Matthias Passlack
Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.
-
公开(公告)号：US11349022B2
公开(公告)日：2022-05-31
申请号：US16889600
申请日：2020-06-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Timothy Vasen , Gerben Doornbos , Matthias Passlack
IPC: H01L29/66 , H01L29/775 , H01L29/205 , H01L29/10 , H01L29/08
Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.
-
Patent Agency Ranking
公开(公告)号：US11271163B2
公开(公告)日：2022-03-08
申请号：US16387640
申请日：2019-04-18
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Martin Christopher Holland , Timothy Vasen , Blandine Duriez
Abstract: In a method, a charged metal dot is deposited on a first position of a surface of a semiconductor substrate. Then, a charged region is formed on a second position of the surface of the semiconductor substrate, thereby establishing of which an electric field direction from the first position toward the second position. The first position is spaced apart from the second position by a distance. Thereafter, a precursor gas flows along the electric field direction on the semiconductor substrate, thereby forming a carbon nanotube (CNT) on the semiconductor substrate.
-
17.发明授权公开(公告)号：US11088246B2
公开(公告)日：2021-08-10
申请号：US16516181
申请日：2019-07-18
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Matthias Passlack , Marcus Johannes Henricus Van Dal , Timothy Vasen , Georgios Vellianitis
Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures each comprising a dielectric layer, a CNT over the dielectric layer, a support layer over the CNT. A sacrificial gate structure is formed over the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source/drain opening, and a source/drain contact layer is formed in the source/drain opening. The source/drain contact is formed such that the source/drain contact is in direct contact with only a part of the CNT and a part of the dielectric layer is disposed between the source/drain contact and the CNT.
-
公开(公告)号：US20210119131A1
公开(公告)日：2021-04-22
申请号：US16656583
申请日：2019-10-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Timothy Vasen , Chao-Ching Cheng , Matthias Passlack , Martin Christopher Holland , Tse-An Chen , Lain-Jong Li
Abstract: A field effect transistor includes a semiconductor substrate, a first pad layer, carbon nanotubes and a gate structure. The first pad layer is disposed over the semiconductor substrate and comprises a 2D material. The carbon nanotubes are disposed over the first insulating pad layer. The gate structure is disposed over the semiconductor substrate and is vertically stacked with the carbon nanotubes. The carbon nanotubes extend from one side to an opposite side of the gate structure.
-
公开(公告)号：US10923659B2
公开(公告)日：2021-02-16
申请号：US16401042
申请日：2019-05-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
IPC: H01L21/00 , H01L51/00 , C23C16/455 , C23C16/56 , H01L23/544 , H01L51/05
Abstract: Provided herein are wafers that can be used to align carbon nanotubes, as well as methods of making and using the same. Such wafers include alignment areas that have four sides and a surface charge, where the alignment areas are surrounded by areas that have a surface charge of a different polarity. Methods of the disclosure may include depositing and selectively etching a number of hardmasks on a substrate. The described methods may also include depositing a carbon nanotube on such a wafer.
-
公开(公告)号：US20200303530A1
公开(公告)日：2020-09-24
申请号：US16889600
申请日：2020-06-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Timothy Vasen , Gerben Doornbos , Matthias Passlack
IPC: H01L29/775 , H01L29/205 , H01L29/66 , H01L29/10 , H01L29/08
Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.
-
-
-
-
-
-
-
-
-
Search Results
31
records
(took 0.023 seconds)
