公开(公告)号：US11984315B2

公开(公告)日：2024-05-14

申请号：US17227905

申请日：2021-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus van Dal ,  Peter Ramvall

IPC: H01L29/00 ,  H01L21/02 ,  H01L27/12 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L21/02181 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02483 ,  H01L21/02614 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/786

Abstract: Structures and methods of forming the same are provided. A structure according to the present disclosure includes an interconnect structure, an aluminum oxide layer over the interconnect structure, and a transistor formed over the aluminum oxide layer. The transistor includes cuprous oxide.

公开(公告)号：US20200311524A1

公开(公告)日：2020-10-01

申请号：US16371382

申请日：2019-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus van Dal ,  Gerben Doornbos ,  Mauricio Manfrini

IPC: G06N3/063 ,  G06N3/04 ,  G11C11/54 ,  G11C13/00

Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first memory element and a second memory element. The memory device includes a substrate and a bottom electrode disposed over the substrate. The first memory element is disposed between the bottom electrode and a top electrode, such that the first memory element has a first area. A second memory element is disposed between the bottom electrode and the top electrode. The second memory element is laterally separated from the first memory element by a non-zero distance. The second memory element has a second area different than the first area.

公开(公告)号：US20200176379A1

公开(公告)日：2020-06-04

申请号：US16525978

申请日：2019-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mauricio Manfrini ,  Marcus Johannes Henricus van Dal

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: The present disclosure relates to an integrated chip including a filament via. In some embodiments, a lower metal layer is disposed over a substrate. A filament dielectric layer is disposed over the lower metal layer. An upper metal layer is disposed over the filament dielectric layer. A filament via is disposed through the filament dielectric layer and electrically connecting the lower metal layer and the upper metal layer. The filament via may be established after other steps of forming the integration chip are finished, therefore making possible barrier-less Cu vias at scaled dimensions. Using the disclosed methods, ultra-scaled vias (e.g. down to 1 nm) can be achieved due to intrinsic character of filament formation mechanism.

公开(公告)号：US20240204106A1

公开(公告)日：2024-06-20

申请号：US18590345

申请日：2024-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Martin Christopher Holland ,  Blandine Duriez ,  Marcus Johannes Henricus van Dal ,  Yasutoshi Okuno

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/267 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/66795

Abstract: In an embodiment, a device includes: a semiconductor substrate having a channel region; a gate stack over the channel region; and an epitaxial source/drain region adjacent the gate stack, the epitaxial source/drain region including: a main portion in the semiconductor substrate, the main portion including a semiconductor material doped with gallium, a first concentration of gallium in the main portion being less than the solid solubility of gallium in the semiconductor material; and a finishing portion over the main portion, the finishing portion doped with gallium, a second concentration of gallium in the finishing portion being greater than the solid solubility of gallium in the semiconductor

公开(公告)号：US20210376107A1

公开(公告)日：2021-12-02

申请号：US16888349

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus van Dal ,  Gerben Doornbos ,  Georgios Vellianitis

IPC: H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first gate electrode, a ferroelectric insulating layer over the first gate electrode, a semiconductor member over the ferroelectric insulating layer, a gate dielectric layer over the semiconductor member, and a second gate electrode over the gate dielectric layer.

公开(公告)号：US10971684B2

公开(公告)日：2021-04-06

申请号：US16412810

申请日：2019-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mauricio Manfrini ,  Chung-Te Lin ,  Gerben Doornbos ,  Marcus Johannes Henricus van Dal

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.

公开(公告)号：US10923659B2

公开(公告)日：2021-02-16

申请号：US16401042

申请日：2019-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Gerben Doornbos ,  Marcus Johannes Henricus van Dal ,  Matthias Passlack

IPC: H01L21/00 ,  H01L51/00 ,  C23C16/455 ,  C23C16/56 ,  H01L23/544 ,  H01L51/05

Abstract: Provided herein are wafers that can be used to align carbon nanotubes, as well as methods of making and using the same. Such wafers include alignment areas that have four sides and a surface charge, where the alignment areas are surrounded by areas that have a surface charge of a different polarity. Methods of the disclosure may include depositing and selectively etching a number of hardmasks on a substrate. The described methods may also include depositing a carbon nanotube on such a wafer.

公开(公告)号：US20200381353A1

公开(公告)日：2020-12-03

申请号：US16668721

申请日：2019-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus van Dal ,  Peter Ramvall

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/20 ,  H01L21/477

Abstract: Structures and methods of forming the same are provided. A structure according to the present disclosure includes an interconnect structure, an aluminum oxide layer over the interconnect structure, and a transistor formed over the aluminum oxide layer. The transistor includes cuprous oxide.

公开(公告)号：US20240297037A1

公开(公告)日：2024-09-05

申请号：US18662267

申请日：2024-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus van Dal ,  Peter Ramvall

IPC: H01L21/02 ,  H01L27/12 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L21/02181 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02483 ,  H01L21/02614 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/786

Abstract: Structures and methods of forming the same are provided. A structure according to the present disclosure includes an interconnect structure, an aluminum oxide layer over the interconnect structure, and a transistor formed over the aluminum oxide layer. The transistor includes cuprous oxide.

公开(公告)号：US20240274474A1

公开(公告)日：2024-08-15

申请号：US18321483

申请日：2023-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus van Dal

IPC: H01L21/8238 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0688 ,  H01L27/0922 ,  H01L27/0924

Abstract: A method includes forming a Complimentary Field-Effect Transistor (CFET) including forming an n-type transistor and a p-type transistor overlapping the n-type transistor. The formation of the n-type transistor includes forming a first channel region comprising a first semiconductor material, and forming an n-type source/drain region on a side of, and connecting to, the first channel region. The formation of the p-type transistor includes forming a second channel region comprising a second semiconductor material different from the first semiconductor material, and forming a p-type source/drain region on a side of, and connecting to, the second channel region.