公开(公告)号：US20190067436A1

公开(公告)日：2019-02-28

申请号：US15690693

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang WU ,  Shiu-Ko JANG-JIAN ,  Ting-Chun WANG ,  Chuan-Pu LIU

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/66 ,  H01L21/768 ,  H01L21/326 ,  H01L21/02 ,  H01L21/285 ,  H01L29/78 ,  H01L29/417 ,  H01L29/165

Abstract: The present disclosure describes a silicide formation process which employs the formation of an amorphous layer in the SiGe S/D region via an application of a substrate bias voltage during a metal deposition process. For example, the method includes a substrate with a gate structure disposed thereon and a source/drain region adjacent to the gate structure. A dielectric is formed over the gate structure and the source-drain region. A contact opening is formed in the dielectric to expose a portion of the gate structure and a portion of the source/drain region. An amorphous layer is formed in the exposed portion of the source/drain region with a thickness and a composition which is based on an adjustable bias voltage applied to the substrate. Further, an anneal is performed to form a silicide on the source/drain region.

公开(公告)号：US20170033199A1

公开(公告)日：2017-02-02

申请号：US14815547

申请日：2015-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta WU ,  Ting-Chun WANG ,  Yuan-Nien CHEN

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/3115

CPC classification number: H01L29/785 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/3115 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor fin, a first silicon nitride based layer, a lining oxide layer, a second silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface. The first silicon nitride based layer peripherally encloses the second side surface of the semiconductor fin. The lining oxide layer is disposed conformal to the first silicon nitride based layer. The second silicon nitride based layer is disposed conformal to the lining oxide layer. The gate oxide layer is disposed conformal to the top surface and the first side surface of the semiconductor fin.

Abstract translation: 半导体器件包括半导体鳍片，第一氮化硅基层，衬里氧化物层，第二氮化硅基层和栅极氧化物层。 半导体翅片具有顶表面，与顶表面相邻的第一侧表面，以及设置在第一侧表面下方并与其邻近的第二侧表面。 第一氮化硅基层周边地包围半导体鳍片的第二侧表面。 内衬氧化物层与第一氮化硅基层一致地设置。 第二氮化硅基层与衬里氧化物层一致地设置。 栅极氧化物层与半导体鳍片的顶面和第一侧面共面配置。

公开(公告)号：US20170032970A1

公开(公告)日：2017-02-02

申请号：US14814370

申请日：2015-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta WU ,  Shiu-Ko JANGJIAN ,  Chung-Ren SUN ,  Ming-Te CHEN ,  Ting-Chun WANG ,  Jun-Jie CHENG

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface. The lining oxide layer peripherally encloses the second side surface of the semiconductor fin. The silicon nitride based layer is disposed conformal to the lining oxide layer. The gate oxide layer is disposed conformal to the top surface and the first side surface.

Abstract translation: 半导体器件包括半导体鳍片，衬里氧化物层，氮化硅基层和栅极氧化物层。 半导体翅片具有顶表面，与顶表面相邻的第一侧表面，以及设置在第一侧表面下方并与其邻近的第二侧表面。 衬里氧化物层周边地包围半导体鳍片的第二侧表面。 氮化硅基层与衬里氧化物层一致地设置。 栅极氧化物层与顶表面和第一侧表面共形设置。

公开(公告)号：US20200176310A1

公开(公告)日：2020-06-04

申请号：US16698528

申请日：2019-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jun-Nan Nian ,  Shiu-Ko JANGJIAN ,  Yu-Ren PENG ,  Yao-Hsiang LIANG ,  Ting-Chun WANG

IPC: H01L21/768 ,  C25D17/00 ,  C25D21/12 ,  C25D3/38

Abstract: A method for performing an electrochemical plating (ECP) process includes contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited, electroplating the metal on the surface of the substrate, in situ monitoring a plating current flowing through the plating solution between an anode and the substrate immersed in the plating solution as the ECP process continues, and adjusting a composition of the plating solution in response to the plating current being below a critical plating current such that voids formed in a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate are prevented.

公开(公告)号：US20170338348A1

公开(公告)日：2017-11-23

申请号：US15660355

申请日：2017-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta WU ,  Shiu-Ko JANGJIAN ,  Cheng-Wei CHEN ,  Ting-Chun WANG

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7854 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848

Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile by the thermal hydrogen treatment.

公开(公告)号：US20160204245A1

公开(公告)日：2016-07-14

申请号：US14677405

申请日：2015-04-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Shiu-Ko JANGJIAN ,  Chi-Cherng JENG ,  Chih-Nan WU ,  Chun-Che LIN ,  Ting-Chun WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/02274 ,  H01L21/0228 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.

Abstract translation: 提供了一种翅片场设备结构及其形成方法。 FinFET器件结构包括从衬底延伸的衬底和鳍结构。 FinFET器件结构还包括形成在衬底上的隔离结构。 翅片结构具有顶部和底部，并且底部嵌入隔离结构中。 FinFET器件结构还包括形成在鳍结构的顶部上的保护层。 界面处于保护层和翅片结构的顶部之间，并且界面的粗糙度在约0.1nm至约2.0nm的范围内。