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公开(公告)号：US20220326443A1
公开(公告)日：2022-10-13
申请号：US17808813
申请日：2022-06-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Weiwei Song , Stefan Rusu , Chewn-Pu Jou , Huan-Neng Chen
Abstract: A method includes etching a silicon layer to form a silicon slab and an upper silicon region over the silicon slab, and implanting the silicon slab and the upper silicon region to form a p-type region, an n-type region, and an intrinsic region between the p-type region and the n-type region. The method further includes etching the p-type region, the n-type region, and the intrinsic region to form a trench. The remaining portions of the upper silicon region form a Multi-Mode Interferometer (MMI) region. An epitaxy process is performed to grow a germanium region in the trench. Electrical connections are made to connect to the p-type region and the n-type region.
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公开(公告)号：US11417596B2
公开(公告)日：2022-08-16
申请号：US16984297
申请日：2020-08-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Weiwei Song , Chan-Hong Chern , Feng-Wei Kuo , Lan-Chou Cho , Stefan Rusu
IPC: H01L23/52 , H01L31/18 , H01L31/0232 , G02B6/43
Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an insulator layer arranged over a substrate. Further, an upper routing structure is arranged over the insulator layer and is made of a semiconductor material. A lower optical routing structure is arranged below the substrate and is embedded in a lower dielectric structure. The integrated chip further includes an anti-reflective layer that is arranged below the substrate and directly contacts the substrate.
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公开(公告)号：US20210271020A1
公开(公告)日：2021-09-02
申请号：US16803153
申请日：2020-02-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mohammed Rabiul Islam , Stefan Rusu , Weiwei Song
Abstract: A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.
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公开(公告)号：US12265258B2
公开(公告)日：2025-04-01
申请号：US18232338
申请日：2023-08-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Weiwei Song , Stefan Rusu , Mohammed Rabiul Islam
Abstract: Structures and methods for high speed interconnection in photonic systems are described herein. In one embodiment, a photonic device is disclosed. The photonic device includes: a substrate; a plurality of metal layers on the substrate; a photonic material layer comprising graphene over the plurality of metal layers; and an optical routing layer comprising a waveguide on the photonic material layer.
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公开(公告)号：US11841561B2
公开(公告)日：2023-12-12
申请号：US17379620
申请日：2021-07-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Weiwei Song , Stefan Rusu , Chan-Hong Chern , Chih-Chang Lin
CPC classification number: G02F1/025 , G02F1/2255 , G02F1/2257 , G02F2201/508 , G02F2201/58
Abstract: A semiconductor device include: a first bus waveguide; a first silicon ring optically coupled to the first bus waveguide; a backup silicon ring optically coupled to the first bus waveguide; a first heater and a second heater configured to heat the first silicon ring and the backup silicon ring, respectively; and a first switch, where the first switch is configured to electrically couple the first silicon ring to a first radio frequency (RF) circuit when the first switch is at a first switching position, and is configured to electrically couple the backup silicon ring to the first RF circuit when the first switch is at a second switching position.
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Patent Agency Ranking
公开(公告)号：US11550102B2
公开(公告)日：2023-01-10
申请号：US17007743
申请日：2020-08-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Weiwei Song , Stefan Rusu , Mohammed Rabiul Islam
Abstract: Structures and methods for high speed interconnection in photonic systems are described herein. In one embodiment, a photonic device is disclosed. The photonic device includes: a substrate; a plurality of metal layers on the substrate; a photonic material layer comprising graphene over the plurality of metal layers; and an optical routing layer comprising a waveguide on the photonic material layer.
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公开(公告)号：US11531159B2
公开(公告)日：2022-12-20
申请号：US17212934
申请日：2021-03-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chan-Hong Chern , Lan-Chou Cho , Huan-Neng Chen , Min-Hsiang Hsu , Feng-Wei Kuo , Chih-Chang Lin , Weiwei Song , Chewn-Pu Jou
Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.
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公开(公告)号：US11378750B2
公开(公告)日：2022-07-05
申请号：US16745561
申请日：2020-01-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Weiwei Song , Stefan Rusu , Chewn-Pu Jou , Huan-Neng Chen
Abstract: A method includes etching a silicon layer to form a silicon slab and an upper silicon region over the silicon slab, and implanting the silicon slab and the upper silicon region to form a p-type region, an n-type region, and an intrinsic region between the p-type region and the n-type region. The method further includes etching the p-type region, the n-type region, and the intrinsic region to form a trench. The remaining portions of the upper silicon region form a Multi-Mode Interferometer (MMI) region. An epitaxy process is performed to grow a germanium region in the trench. Electrical connections are made to connect to the p-type region and the n-type region.
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公开(公告)号：US20210396930A1
公开(公告)日：2021-12-23
申请号：US17212934
申请日：2021-03-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chan-Hong Chern , Lan-Chou Cho , Huan-Neng Chen , Min Hsiang Hsu , Feng-Wei Kuo , Chih-Chang Lin , Weiwei Song , Chewn-Pu Jou
Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the second waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.
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公开(公告)号：US20210193564A1
公开(公告)日：2021-06-24
申请号：US16984297
申请日：2020-08-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Weiwei Song , Chan-Hong Chern , Feng-Wei Kuo , Lan-Chou Cho , Stefan Rusu
IPC: H01L23/52 , G02B6/43 , H01L31/0232 , H01L31/18
Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an insulator layer arranged over a substrate. Further, an upper routing structure is arranged over the insulator layer and is made of a semiconductor material. A lower optical routing structure is arranged below the substrate and is embedded in a lower dielectric structure. The integrated chip further includes an anti-reflective layer that is arranged below the substrate and directly contacts the substrate.
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