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公开(公告)号：US20230389255A1
公开(公告)日：2023-11-30
申请号：US18446546
申请日：2023-08-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Po-Sheng WANG , Yangsyu Lin , Cheng Hung Lee
IPC: H10B10/00 , G11C11/419 , G11C11/412
CPC classification number: H10B10/12 , G11C11/419 , G11C11/412 , H10B10/18
Abstract: The present disclosure describes embodiments of a memory device with a pre-charge circuit. The memory device can include a memory cell, and the pre-charge circuit can include a first transistor and a second transistor. The first transistor includes a first gate terminal, a first source/drain (S/D) terminal coupled to a reference voltage, and a second S/D terminal coupled to a first terminal of the memory cell. The second transistor includes a second gate terminal, a third S/D terminal coupled to the reference voltage, and a fourth S/D terminal coupled to the second terminal of the memory cell. The first and second transistors are configured to pass the reference voltage in response to the control signal being applied to the first and second gate terminals, respectively.
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公开(公告)号：US11264066B2
公开(公告)日：2022-03-01
申请号：US16999867
申请日：2020-08-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shang-Chi Wu , Cheng Hung Lee , Chien-Kuo Su , Chiting Cheng , Yu-Hao Hsu , Yangsyu Lin
Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices. This specialized circuitry, also referred to as a write driver, writes the electronic data onto these data lines for storage in the one or more memory cells during the write mode of operation.
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公开(公告)号：US10818677B2
公开(公告)日：2020-10-27
申请号：US16502790
申请日：2019-07-03
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yangsyu Lin , Chi-Lung Lee , Chien-Chi Tien , Chiting Cheng
IPC: H01L27/11 , H01L27/02 , H01L27/092 , G11C11/419 , H01L23/522 , G11C11/412 , H01L23/528
Abstract: A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.
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公开(公告)号：US20200020387A1
公开(公告)日：2020-01-16
申请号：US16580675
申请日：2019-09-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yangsyu Lin , Chiting Cheng
IPC: G11C11/417 , H01L27/11 , H01L23/528 , G11C5/14
Abstract: A dual rail device includes a first power domain circuit coupled to a first power supply through a first header control switch and a second power domain circuit coupled to a second power supply. The first and second power supplies have different steady-state voltage levels. The first power domain circuit is interfaced to the second power domain circuit. The device also includes a power detector circuit for providing a control signal for the first header control switch responsive to a voltage level of the second power supply.
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公开(公告)号：US20190004718A1
公开(公告)日：2019-01-03
申请号：US15938502
申请日：2018-03-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Hao HSU , Cheng Hung Lee , Chen-Lin Yang , Chiting Cheng , Fu-An Wu , Hung-Jen Liao , Jung-Ping Yang , Jonathan Tsung-Yung Chang , Wei Min Chan , Yen-Huei Chen , Yangsyu Lin , Chien-Chen Lin
IPC: G06F3/06 , G11C11/4074 , G11C16/12 , G11C16/30 , G11C5/14
Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to control minimize power consumption.
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Patent Agency Ranking
公开(公告)号：US11728789B2
公开(公告)日：2023-08-15
申请号：US17406273
申请日：2021-08-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia-Chen Kuo , Yangsyu Lin , Yu-Hao Hsu , Cheng Hung Lee , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC: H03K3/012
CPC classification number: H03K3/012
Abstract: The present disclosure describes an example circuit for selecting a voltage supply. The circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.
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公开(公告)号：US11651133B2
公开(公告)日：2023-05-16
申请号：US17031547
申请日：2020-09-24
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Po-Sheng Wang , Chao Yuan Cheng , Chien-Chi Tien , Yangsyu Lin
IPC: G06F30/392 , H01L27/02 , H01L27/118 , G06F119/18
CPC classification number: G06F30/392 , H01L27/0207 , H01L27/11807 , G06F2119/18 , H01L2027/11824 , H01L2027/11881
Abstract: A method of forming an integrated circuit includes placing a first cell layout design of the integrated circuit on a layout design, and manufacturing the integrated circuit based on the layout design. Placing the first cell layout design includes placing a first active region layout pattern adjacent to a first cell boundary, placing a second active region layout pattern adjacent to a second cell boundary, and placing a first set of active region layout patterns between the first and second active region layout patterns, according to a first set of guidelines. The first set of guidelines includes selecting transistors of a first type with a first driving strength and transistors of a second type with a second driving strength. In some embodiments, the first, second and first set of active region layout patterns extend in the first direction, and are on a first layout level.
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公开(公告)号：US20170040042A1
公开(公告)日：2017-02-09
申请号：US14980287
申请日：2015-12-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hektor Huang , Yangsyu Lin , Yu-Hao Hsu , Chia-En Huang , Chiting Cheng , Chen-Lin Yang , Jung-Ping Yang , Cheng Hung Lee
Abstract: A power management circuit for an electronic device is disclosed that sequentially activates and/or deactivates electronic circuits of the electronic device. The power management circuit provides a first group of one or more circuit power management signals to activate and/or deactivate a first electronic circuit from among the electronic circuits. Thereafter, the power management circuit provides a corresponding power management signal from among a second group of the one or more circuit power management signals that corresponds to a portion of the first electronic circuit that has been activated and/or deactivated by the first group of the one or more circuit power management signals to activate and/or deactivate a portion of a second electronic circuit from among the electronic circuits. The power management circuit continues to sequentially provide each of the one or more circuit power management signals in a similar manner until the electronic circuits of the electronic device have been activated and/or deactivated.
Abstract translation: 公开了一种用于电子设备的电源管理电路，其顺序地激活和/或去激活电子设备的电子电路。 功率管理电路提供第一组一个或多个电路功率管理信号以激活和/或去激活来自电子电路之间的第一电子电路。 此后，电源管理电路从一个或多个电路电源管理信号的第二组中提供相应的功率管理信号，其对应于已经被第一组的第一组激活和/或去激活的第一电子电路的一部分 一个或多个电路功率管理信号，用于激活和/或去激活来自电子电路的第二电子电路的一部分。 功率管理电路以类似的方式继续顺序提供一个或多个电路功率管理信号中的每一个，直到电子设备的电子电路已经被激活和/或去激活为止。
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公开(公告)号：US10762934B2
公开(公告)日：2020-09-01
申请号：US16263904
申请日：2019-01-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shang-Chi Wu , Cheng Hung Lee , Chien-Kuo Su , Chiting Cheng , Yu-Hao Hsu , Yangsyu Lin
Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices. This specialized circuitry, also referred to as a write driver, writes the electronic data onto these data lines for storage in the one or more memory cells during the write mode of operation.
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公开(公告)号：US20190172523A1
公开(公告)日：2019-06-06
申请号：US16181889
申请日：2018-11-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yangsyu Lin , Chiting Cheng
IPC: G11C11/417 , G11C5/14 , H01L23/528 , H01L27/11
Abstract: A dual rail device includes a first power domain circuit coupled to a first power supply through a first header control switch and a second power domain circuit coupled to a second power supply. The first and second power supplies have different steady-state voltage levels. The first power domain circuit is interfaced to the second power domain circuit. The device also includes a power detector circuit for providing a control signal for the first header control switch responsive to a voltage level of the second power supply.
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