公开(公告)号：US20210391248A1

公开(公告)日：2021-12-16

申请号：US16900289

申请日：2020-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Te Huang ,  Yung-Shih Cheng

IPC: H01L23/522 ,  H01L23/64 ,  H01L21/308 ,  H01L21/768 ,  H01L49/02

Abstract: A method includes forming a first electrode layer having a first opening, with the first opening having a first lateral dimension, forming a first capacitor insulator over the first electrode layer, and forming a second electrode layer over the first capacitor insulator, with the second electrode layer having a second opening. The first opening is directly underlying the second opening. The second opening has a second lateral dimension greater than the first lateral dimension. The method further includes depositing a dielectric layer over the second electrode layer, and forming a contact opening, which comprises a first portion including the first opening, and a second portion including the second opening. A conductive plug is formed in the contact opening.

公开(公告)号：US20140231967A1

公开(公告)日：2014-08-21

申请号：US13771382

申请日：2013-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chuan Teng ,  Jung-Huei Peng ,  Shang-Ying Tsai ,  Hsin-Ting Huang ,  Lin-Min Hung ,  Yao-Te Huang ,  Chin-Yi Cho

IPC: H01L21/18 ,  H01L29/06

CPC classification number: H01L21/185 ,  B81C1/00269 ,  B81C2201/053 ,  B81C2203/0118 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/564 ,  H01L29/06 ,  H01L2224/94 ,  H01L2924/18161 ,  H01L2224/83

Abstract: A method for fabricating a semiconductor device is disclosed. A first substrate is arranged over a second substrate. A wafer bonding process is performed on the semiconductor device. First regions of the device are enclosed by the bonding process. Second regions of the device remain exposed. One or more processes are performed on the exposed second regions, after performing the wafer bonding process. The one or more processes include a fill process that forms a fill material within the exposed second regions. An edge seal material is applied on the first and second substrates after performing the one or more processes.

Abstract translation: 公开了一种制造半导体器件的方法。 第一衬底被布置在第二衬底上。 在半导体器件上进行晶片接合处理。 设备的第一个区域由绑定过程包围。 设备的第二个区域保持暴露。 在进行晶片接合处理之后，在暴露的第二区域上执行一个或多个处理。 一个或多个过程包括在暴露的第二区域内形成填充材料的填充过程。 在执行一个或多个处理之后，在第一和第二基板上施加边缘密封材料。

公开(公告)号：US12142574B2

公开(公告)日：2024-11-12

申请号：US17390104

申请日：2021-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Te Huang ,  Hong-Wei Chan ,  Yung-Shih Cheng ,  Jiing-Feng Yang ,  Hui Lee

IPC: H01L23/544 ,  H01L21/768 ,  H01L23/522

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming an interconnect structure over a device wafer. The device wafer includes a first integrated circuit, a semiconductor substrate, and a redistribution structure. The method further includes forming a metallization layer and a group of dummy insertion structures having a stepped pattern density in a topmost dielectric layer of the interconnect structure. The group of dummy insertion structures and the metallization layer are planarized with the dielectric layer. The method further includes forming a first bonding layer over the group of dummy insertion structures, the metallization layer, and the dielectric layer. The method further includes bonding a carrier wafer to the first bonding layer, forming an opening through the semiconductor substrate, and forming a conductive via in the opening and electrically coupled to the redistribution structure.

公开(公告)号：US20240145430A1

公开(公告)日：2024-05-02

申请号：US18410060

申请日：2024-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Te Huang ,  Hong-Wei Chan ,  Yung-Shih Cheng

IPC: H01L23/00 ,  H01L23/528

CPC classification number: H01L24/83 ,  H01L23/5283 ,  H01L24/27 ,  H01L24/32 ,  H01L2224/27452 ,  H01L2224/2784 ,  H01L2224/32225 ,  H01L2224/83005 ,  H01L2224/83201 ,  H01L2924/37001

Abstract: In an embodiment, a method includes performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure; performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition; planarizing the first bonding layer; forming a second bonding layer over a second substrate; pressing the second bonding layer onto the first bonding layer; and removing the first s

公开(公告)号：US20220310527A1

公开(公告)日：2022-09-29

申请号：US17390104

申请日：2021-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Yao-Te Huang ,  Hong-Wei Chan ,  Yung-Shih Cheng ,  Jiing-Feng Yang ,  Hui Lee

IPC: H01L23/544 ,  H01L23/522 ,  H01L21/768

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming an interconnect structure over a device wafer. The device wafer includes a first integrated circuit, a semiconductor substrate, and a redistribution structure. The method further includes forming a metallization layer and a group of dummy insertion structures having a stepped pattern density in a topmost dielectric layer of the interconnect structure. The group of dummy insertion structures and the metallization layer are planarized with the dielectric layer. The method further includes forming a first bonding layer over the group of dummy insertion structures, the metallization layer, and the dielectric layer. The method further includes bonding a carrier wafer to the first bonding layer, forming an opening through the semiconductor substrate, and forming a conductive via in the opening and electrically coupled to the redistribution structure.

公开(公告)号：US09269679B2

公开(公告)日：2016-02-23

申请号：US14072141

申请日：2013-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chuan Teng ,  Jung-Huei Peng ,  Shang-Ying Tsai ,  Li-Min Hung ,  Yao-Te Huang ,  Chin-Yi Cho

IPC: H01L21/66 ,  H01L23/00 ,  B81C99/00

CPC classification number: H01L24/06 ,  B81B2207/012 ,  B81C99/0045 ,  B81C99/005 ,  H01L22/32 ,  H01L23/10 ,  H01L24/32 ,  H01L24/94 ,  H01L2224/0605 ,  H01L2224/32145 ,  H01L2224/83194 ,  H01L2924/01322 ,  H01L2924/16235 ,  H01L2924/00

Abstract: In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.

Abstract translation: 在用于MEMS器件的晶片级芯片级封装技术中，首先在CMOS衬底的两个CMOS器件之间的刻划线区域上蚀刻深沟槽。 在将CMOS衬底与MEMS衬底结合之后，通过薄层化工艺来打开深沟槽，使得在衬底不是（部分单片化）的情况下将CMOS衬底分离。 MEMS基板上的电测试板被暴露，保护材料可以通过粘结层周围的深沟槽填充。 在填充保护材料之后，将晶片切割成形成封装的独立芯片，保护结合层外部的环境。

公开(公告)号：US08841201B2

公开(公告)日：2014-09-23

申请号：US13771382

申请日：2013-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chuan Teng ,  Jung-Huei Peng ,  Shang-Ying Tsai ,  Hsin-Ting Huang ,  Lin-Min Hung ,  Yao-Te Huang ,  Chin-Yi Cho

IPC: H01L21/46 ,  H01L29/06 ,  H01L21/18

CPC classification number: H01L21/185 ,  B81C1/00269 ,  B81C2201/053 ,  B81C2203/0118 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/564 ,  H01L29/06 ,  H01L2224/94 ,  H01L2924/18161 ,  H01L2224/83

Abstract: A method for fabricating a semiconductor device is disclosed. A first substrate is arranged over a second substrate. A wafer bonding process is performed on the semiconductor device. First regions of the device are enclosed by the bonding process. Second regions of the device remain exposed. One or more processes are performed on the exposed second regions, after performing the wafer bonding process. The one or more processes include a fill process that forms a fill material within the exposed second regions. An edge seal material is applied on the first and second substrates after performing the one or more processes.

Abstract translation: 公开了一种制造半导体器件的方法。 第一衬底被布置在第二衬底上。 在半导体器件上进行晶片接合处理。 设备的第一个区域由绑定过程包围。 设备的第二个区域保持暴露。 在进行晶片接合处理之后，在暴露的第二区域上执行一个或多个处理。 一个或多个过程包括在暴露的第二区域内形成填充材料的填充过程。 在执行一个或多个处理之后，在第一和第二基板上施加边缘密封材料。