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1.发明申请STRUCTURE AND METHOD TO MITIGATE SOLDERING OFFSET FOR WAFER-LEVEL CHIP SCALE PACKAGE (WLCSP) APPLICATIONS 审中-公开用于降低水平芯片尺寸封装（WLCSP）应用的焊接偏移的结构和方法公开(公告)号：US20160264402A1
公开(公告)日：2016-09-15
申请号：US14645650
申请日：2015-03-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shao-Chi Yu , Chia-Ming Hung , Hsin-Ting Huang , Hsiang-Fu Chen , Allen Timothy Chang , Wen-Chuan Tai
CPC classification number: B81C1/0023 , B81B7/0048 , B81B7/0051 , B81B7/0054 , B81B7/007 , H01L2224/04026 , H01L2224/05624 , H01L2224/05644 , H01L2224/16225 , H01L2224/2957 , H01L2224/29624 , H01L2224/29644
Abstract: The present disclosure relates to a wafer level chip scale package (WLCSP) with a stress absorbing cap substrate. The cap substrate is bonded to a die through a bond ring and a bond pad arranged on an upper surface of the cap substrate. A through substrate via (TSV) extends from the bond pad, through the cap substrate, to a lower surface of the cap substrate. Further, recesses in the upper surface extend around the bond pad and along sidewalls of the bond ring. The recesses absorb induced stress, thereby mitigating any device offset in the die.
Abstract translation: 本公开涉及一种具有应力吸收帽基片的晶片级芯片级封装（WLCSP）。 盖基板通过结合环和布置在盖基板的上表面上的接合焊盘接合到管芯。 贯穿衬底通孔（TSV）从接合焊盘延伸穿过盖衬底到帽衬底的下表面。 此外，上表面中的凹槽围绕接合焊盘延伸并且沿着接合环的侧壁延伸。 凹槽吸收诱发的应力，从而减轻模具中的任何装置偏移。
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公开(公告)号：US20160016789A1
公开(公告)日：2016-01-21
申请号：US14332461
申请日：2014-07-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shao-Chi Yu , Hsiang-Fu Chen , Hsin-Ting Huang , Chia-Ming Hung , Wen-Chuan Tai
CPC classification number: B81C1/00293 , B81B2207/092 , B81B2207/095 , B81B2207/096 , B81C2203/0109 , B81C2203/0136
Abstract: The present disclosure relates to a MEMS device with a hermetic sealing structure, and an associated method. In some embodiments, a first die and a second die are bonded at a bond interface region to form a chamber. A conformal thin film structure is disposed covering an outer sidewall of the bond interface region to provide hermetic sealing. In some embodiments, the conformal thin film structure is a continuous thin layer covering an outer surface of the second die and a top surface of the first die. In some other embodiments, the conformal thin film structure comprises several discrete thin film patches disposed longitudinal.
Abstract translation: 本公开涉及一种具有气密密封结构的MEMS器件及其相关方法。 在一些实施例中，第一管芯和第二管芯在结合界面区域结合形成腔室。 设置覆盖接合界面区域的外侧壁的保形薄膜结构以提供气密密封。 在一些实施例中，保形薄膜结构是覆盖第二模具的外表面和第一模具的顶表面的连续薄层。 在一些其它实施例中，保形薄膜结构包括纵向布置的几个分立的薄膜贴片。
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公开(公告)号：US20140231967A1
公开(公告)日：2014-08-21
申请号：US13771382
申请日：2013-02-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Chuan Teng , Jung-Huei Peng , Shang-Ying Tsai , Hsin-Ting Huang , Lin-Min Hung , Yao-Te Huang , Chin-Yi Cho
CPC classification number: H01L21/185 , B81C1/00269 , B81C2201/053 , B81C2203/0118 , H01L21/561 , H01L21/563 , H01L23/3135 , H01L23/3185 , H01L23/564 , H01L29/06 , H01L2224/94 , H01L2924/18161 , H01L2224/83
Abstract: A method for fabricating a semiconductor device is disclosed. A first substrate is arranged over a second substrate. A wafer bonding process is performed on the semiconductor device. First regions of the device are enclosed by the bonding process. Second regions of the device remain exposed. One or more processes are performed on the exposed second regions, after performing the wafer bonding process. The one or more processes include a fill process that forms a fill material within the exposed second regions. An edge seal material is applied on the first and second substrates after performing the one or more processes.
Abstract translation: 公开了一种制造半导体器件的方法。 第一衬底被布置在第二衬底上。 在半导体器件上进行晶片接合处理。 设备的第一个区域由绑定过程包围。 设备的第二个区域保持暴露。 在进行晶片接合处理之后，在暴露的第二区域上执行一个或多个处理。 一个或多个过程包括在暴露的第二区域内形成填充材料的填充过程。 在执行一个或多个处理之后，在第一和第二基板上施加边缘密封材料。
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公开(公告)号：US09714166B2
公开(公告)日：2017-07-25
申请号：US14332461
申请日：2014-07-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shao-Chi Yu , Hsiang-Fu Chen , Hsin-Ting Huang , Chia-Ming Hung , Wen-Chuan Tai
CPC classification number: B81C1/00293 , B81B2207/092 , B81B2207/095 , B81B2207/096 , B81C2203/0109 , B81C2203/0136
Abstract: The present disclosure relates to a MEMS device with a hermetic sealing structure, and an associated method. In some embodiments, a first die and a second die are bonded at a bond interface region to form a chamber. A conformal thin film structure is disposed covering an outer sidewall of the bond interface region to provide hermetic sealing. In some embodiments, the conformal thin film structure is a continuous thin layer covering an outer surface of the second die and a top surface of the first die. In some other embodiments, the conformal thin film structure comprises several discrete thin film patches disposed longitudinal.
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公开(公告)号：US20170121174A1
公开(公告)日：2017-05-04
申请号：US15406915
申请日：2017-01-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia-Ming Hung , Shao-Chi Yu , Hsiang-Fu Chen , Wen-Chuan Tai , Hsin-Ting Huang
CPC classification number: B81C1/00238 , B81B7/0038 , B81B7/0061 , B81B2201/0264 , B81B2203/0315 , B81C2203/0136 , B81C2203/0145 , B81C2203/019 , B81C2203/036
Abstract: A method for manufacturing a microelectromechanical systems (MEMS) device is provided. According to some embodiments of the method, a semiconductor structure is provided. The semiconductor structure includes an integrated circuit (IC) substrate, a dielectric layer arranged over the IC substrate, and a MEMS substrate arranged over the IC substrate and the dielectric layer to define a cavity between the MEMS substrate and the IC substrate. The MEMS substrate includes a MEMS hole in fluid communication with the cavity and extending through the MEMS substrate. A sealing layer is formed over or lining the MEMS hole to hermetically seal the cavity with a reference pressure while the semiconductor structure is arranged within a vacuum having the reference pressure. The semiconductor structure resulting from application of the method is also provided.
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Patent Agency Ranking
6.发明授权Microelectrochemical systems (MEMS) device having a seal layer arranged over or lining a hole in fluid communication with a cavity of the MEMS device 有权具有密封层的微电化学系统（MEMS）装置，该密封层布置在与MEMS装置的空腔流体连通的孔中或衬里公开(公告)号：US09567204B2
公开(公告)日：2017-02-14
申请号：US14472636
申请日：2014-08-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia-Ming Hung , Shao-Chi Yu , Hsiang-Fu Chen , Wen-Chuan Tai , Hsin-Ting Huang
CPC classification number: B81C1/00238 , B81B7/0038 , B81B7/0061 , B81B2201/0264 , B81B2203/0315 , B81C2203/0136 , B81C2203/0145 , B81C2203/019 , B81C2203/036
Abstract: A method for manufacturing a microelectromechanical systems (MEMS) device is provided. According to the method, a semiconductor structure is provided. The semiconductor structure includes an integrated circuit (IC) substrate, a dielectric layer arranged over the IC substrate, and a MEMS substrate arranged over the IC substrate and the dielectric layer to define a cavity between the MEMS substrate and the IC substrate. The MEMS substrate includes a MEMS hole in fluid communication with the cavity and extending through the MEMS substrate. A sealing layer is formed over or lining the MEMS hole to hermetically seal the cavity with a reference pressure while the semiconductor structure is arranged within a vacuum having the reference pressure. The semiconductor structure resulting from application of the method is also provided.
Abstract translation: 提供了一种用于制造微机电系统（MEMS）装置的方法。 根据该方法，提供半导体结构。 半导体结构包括集成电路（IC）衬底，布置在IC衬底上的电介质层和布置在IC衬底和电介质层上的MEMS衬底，以在MEMS衬底和IC衬底之间限定空腔。 MEMS衬底包括与空腔流体连通并延伸穿过MEMS衬底的MEMS孔。 在半导体结构布置在具有参考压力的真空中之前，密封层形成在MEMS孔的上方或衬套上，以密封空腔与参考压力。 还提供了由应用该方法得到的半导体结构。
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公开(公告)号：US10131540B2
公开(公告)日：2018-11-20
申请号：US14645650
申请日：2015-03-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shao-Chi Yu , Chia-Ming Hung , Hsin-Ting Huang , Hsiang-Fu Chen , Allen Timothy Chang , Wen-Chuan Tai
Abstract: The present disclosure relates to a wafer level chip scale package (WLCSP) with a stress absorbing cap substrate. The cap substrate is bonded to a die through a bond ring and a bond pad arranged on an upper surface of the cap substrate. A through substrate via (TSV) extends from the bond pad, through the cap substrate, to a lower surface of the cap substrate. Further, recesses in the upper surface extend around the bond pad and along sidewalls of the bond ring. The recesses absorb induced stress, thereby mitigating any device offset in the die.
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公开(公告)号：US20170233249A1
公开(公告)日：2017-08-17
申请号：US15585805
申请日：2017-05-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsin-Ting Huang , Hsiang-Fu Chen , Wen-Chuan Tai , Shao-Chi Yu , Chia-Ming Hung , Allen Timothy Chang , Bruce C.S. Chou , Chin-Min Lin
CPC classification number: B81C1/00285 , B81B7/02 , B81B2201/0235 , B81B2201/0242 , B81B2207/095 , B81B2207/096 , B81C2203/0145
Abstract: The present disclosure relates to a method of forming a micro-electro mechanical system (MEMs) structure. In some embodiments, the method may be performed by providing a device substrate having a first MEMS device and a second MEMS device, and by providing a capping structure having a first cavity and a second cavity. The capping structure is bonded to the device substrate, such that the first cavity is arranged over the first MEMS device and the second cavity is arranged over the second MEMS device. A first pressure is established within the first cavity and the second cavity. A vent is selectively etched within the capping structure to change the first pressure within the second cavity to a second pressure, which is different from the first pressure.
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公开(公告)号：US09856139B2
公开(公告)日：2018-01-02
申请号：US15585805
申请日：2017-05-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsin-Ting Huang , Hsiang-Fu Chen , Wen-Chuan Tai , Shao-Chi Yu , Chia-Ming Hung , Allen Timothy Chang , Bruce C. S. Chou , Chin-Min Lin
CPC classification number: B81C1/00285 , B81B7/02 , B81B2201/0235 , B81B2201/0242 , B81B2207/095 , B81B2207/096 , B81C2203/0145
Abstract: The present disclosure relates to a method of forming a micro-electro mechanical system (MEMs) structure. In some embodiments, the method may be performed by providing a device substrate having a first MEMS device and a second MEMS device, and by providing a capping structure having a first cavity and a second cavity. The capping structure is bonded to the device substrate, such that the first cavity is arranged over the first MEMS device and the second cavity is arranged over the second MEMS device. A first pressure is established within the first cavity and the second cavity. A vent is selectively etched within the capping structure to change the first pressure within the second cavity to a second pressure, which is different from the first pressure.
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公开(公告)号：US09845236B2
公开(公告)日：2017-12-19
申请号：US14645826
申请日：2015-03-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shao-Chi Yu , Chia-Ming Hung , Hsin-Ting Huang , Hsiang-Fu Chen , Allen Timothy Chang , Wen-Chuan Tai
CPC classification number: B81C1/00269 , B81B7/02 , B81B2201/0214 , B81B2201/0264 , B81B2201/0278 , B81B2207/096 , B81C2203/0109 , G01K13/00 , G01L9/0073 , G01L19/0092 , G01N27/221 , G01N2027/222
Abstract: The present disclosure is directed to a monolithic MEMS (micro-electromechanical system) platform having a temperature sensor, a pressure sensor and a gas sensor, and an associated method of formation. In some embodiments, the MEMS platform includes a semiconductor substrate having one or more transistor devices and a temperature sensor. A dielectric layer is disposed over the semiconductor substrate. A cavity is disposed within an upper surface of the dielectric layer. A MEMS substrate is arranged onto the upper surface of the dielectric layer and has a first section and a second section. A pressure sensor has a first pressure sensor electrode that is vertically separated by the cavity from a second pressure sensor electrode within the first section of a MEMS substrate. A gas sensor has a polymer disposed between a first gas sensor electrode within the second section of a MEMS substrate and a second gas sensor electrode.
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