公开(公告)号：US09865477B2

公开(公告)日：2018-01-09

申请号：US15052310

申请日：2016-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hung Chen ,  Chia-Jung Hsu ,  Yi-An Lin

IPC: H01L21/321 ,  H01L21/02 ,  H01L21/683 ,  H01L21/673

CPC classification number: H01L21/32115 ,  B24B37/00 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/02054 ,  H01L21/0209 ,  H01L21/3212 ,  H01L21/673 ,  H01L21/683

Abstract: The present disclosure provides a semiconductor fabrication apparatus in accordance with one embodiment. The apparatus includes a wafer stage that is operable to secure and rotate a wafer; a polish head configured to polish a backside surface of the wafer; an air bearing module configured to apply an air pressure to a front surface of the wafer; and an edge sealing unit configured to seal edges of the wafer.

公开(公告)号：US20140256124A1

公开(公告)日：2014-09-11

申请号：US13792258

申请日：2013-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Chia-Jung Hsu ,  Gin-Chen Huang ,  Yi-An Lin ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L29/40

CPC classification number: H01L29/401 ,  B24B37/042 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/67207 ,  H01L21/67219

Abstract: A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (CMP) processes to planarize the formed gate structure using a CMP tool. An in situ gate etching process is performed in a CMP cleaner of the CMP tool to form a gate recess. A contact etch stop layer (CESL) can then be deposited in the formed gate recess and one or more CMP processes performed to planarize the CESL.

Abstract translation: 一种制造金属栅极结构的方法。 该方法包括在半导体衬底之上形成栅极结构，并执行一个或多个化学金属平面化（CMP）工艺，以使用CMP工具对形成的栅极结构进行平坦化。 在CMP工具的CMP清洁器中执行原位栅极蚀刻工艺以形成栅极凹槽。 然后可以将接触蚀刻停止层（CESL）沉积在所形成的栅极凹部中，并执行一个或多个CMP工艺以平坦化CESL。