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11.发明申请公开(公告)号：US20150053925A1
公开(公告)日：2015-02-26
申请号：US13974095
申请日：2013-08-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Shao Liu , Fei-Lung Lai , Chun-Wen Cheng
IPC: G01N27/414 , H01L29/66
CPC classification number: G01N27/4145 , H01L29/66439 , H01L29/775
Abstract: The present disclosure relates to a top-down method of forming a nanowire structure extending between source and drain regions of a nanowire transistor device, and an associated apparatus. In some embodiments, the method provides a substrate having a device layer disposed over a first dielectric layer. The device layer has a source region and a drain region separated by a device material. The first dielectric layer has an embedded gate structure abutting the device layer. One or more masking layers are selectively formed over the device layer to define a nanowire structure. The device layer is then selectively etched according to the one or more masking layers to form a nanowire structure at a position between the source region and the drain region. By forming the nanowire structure through a masking and etch process, the nanowire structure is automatically connected to the source and drain regions.
Abstract translation: 本发明涉及形成在纳米线晶体管器件的源极和漏极区域之间延伸的纳米线结构的自顶向下的方法，以及相关联的器件。 在一些实施例中，该方法提供了具有设置在第一介电层上的器件层的衬底。 器件层具有由器件材料分离的源极区域和漏极区域。 第一电介质层具有邻接器件层的嵌入式栅极结构。 选择性地在器件层上形成一个或多个掩模层以限定纳米线结构。 然后根据一个或多个掩模层选择性地蚀刻器件层，以在源极区域和漏极区域之间的位置处形成纳米线结构。 通过掩模和蚀刻工艺形成纳米线结构，纳米线结构自动连接到源区和漏区。
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公开(公告)号：US11027310B2
公开(公告)日：2021-06-08
申请号：US15355273
申请日：2016-11-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Wen Cheng , Jung-Huei Peng , Yi-Shao Liu , Fei-Lung Lai , Shang-Ying Tsai
Abstract: The present disclosure relates to a method of depositing a fluid onto a substrate. In some embodiments, the method may be performed by mounting a substrate to a micro-fluidic probe card, so that the substrate abuts a cavity within the micro-fluidic probe card that is in communication with a fluid inlet and a fluid outlet. A first fluidic chemical is selectively introduced into the cavity via the fluid inlet of the micro-fluidic probe card.
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公开(公告)号：US10509008B2
公开(公告)日：2019-12-17
申请号：US14700133
申请日：2015-04-29
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Ta-Chuan Liao , Chien-Kuo Yang , Yi-Shao Liu , Tung-Tsun Chen , Chan-Ching Lin , Jui-Cheng Huang , Felix Ying-Kit Tsui , Jing-Hwang Yang
IPC: G01N27/414
Abstract: A biological device includes a substrate, a gate electrode, and a sensing well. The substrate includes a source region, a drain region, a channel region, a body region, and a sensing region. The channel region is disposed between the source region and the drain region. The sensing region is at least disposed between the channel region and the body region. The gate electrode is at least disposed on or above the channel region of the substrate. The sensing well is at least disposed adjacent to the sensing region.
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公开(公告)号：US20190056348A1
公开(公告)日：2019-02-21
申请号：US16165748
申请日：2018-10-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Shao Liu , Jui-Cheng Huang , Tung-Tsun Chen
IPC: G01N27/414 , H01L27/16 , H01L27/085
CPC classification number: G01N27/4148 , G01N27/4145 , H01L23/345 , H01L27/0211 , H01L27/085 , H01L27/16
Abstract: A method of manufacturing an integrated circuit device includes providing a substrate comprising a semiconductor active layer, and forming source/drain regions, temperature sensors, and heating elements either in the semiconductor active layer or on the front side of the semiconductor active layer. The semiconductor active layer has channel regions between adjacent source/drain regions, and each of the heating elements is aligned over at least a portion of a corresponding temperature sensor. The method also includes forming a metal interconnect structure over the front side of the semiconductor active layer and exposing the channel regions from the back side of the semiconductor active layer substrate. A fluid gate dielectric layer is formed over the exposed channel regions.
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公开(公告)号：US10155244B2
公开(公告)日：2018-12-18
申请号：US14027368
申请日：2013-09-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Wen Cheng , Jung-Huei Peng , Yi-Shao Liu , Fei-Lung Lai , Shang-Ying Tsai
Abstract: The present disclosure relates to a micro-fluidic probe card that deposits a fluidic chemical onto a substrate with a minimal amount of fluidic chemical waste, and an associated method of operation. In some embodiments, the micro-fluidic probe card has a probe card body with a first side and a second side. A sealant element, which contacts a substrate, is connected to the second side of the probe card body in a manner that forms a cavity within an interior of the sealant element. A fluid inlet, which provides a fluid from a processing tool to the cavity, is a first conduit extending between the first side and the second side of the probe card body. A fluid outlet, which removes the fluid from the cavity, is a second conduit extending between the first side and the second side of the probe card body.
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Patent Agency Ranking
公开(公告)号：US20170322177A1
公开(公告)日：2017-11-09
申请号：US15661798
申请日：2017-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Alexander Kalnitsky , Yi-Shao Liu , Kai-Chih Liang , Chia-Hua Chu , Chun-Ren Cheng , Chun-Wen Cheng
IPC: G01N27/414 , H01L21/84 , H01L51/00 , H01L27/12
CPC classification number: G01N27/4145 , G01N27/414 , G01N27/4148 , H01L21/84 , H01L27/1203 , H01L51/0093
Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.
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公开(公告)号：US20170219520A1
公开(公告)日：2017-08-03
申请号：US15492548
申请日：2017-04-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
Inventor： Yi-Shao Liu , Jui-Cheng Huang , Tung-Tsun Chen
IPC: G01N27/414 , H01L23/34 , H01L27/16
CPC classification number: G01N27/4148 , G01N27/4145 , H01L23/345 , H01L27/0211 , H01L27/085 , H01L27/16
Abstract: A device layer of an integrated circuit device includes a semiconductor active layer spanning a plurality of device regions. Each of the device regions has a heating element, a temperature sensor, and bioFETs in the device layer. The bioFETs have source/drain regions and channel regions in the semiconductor active layer and fluid gates exposed on a surface for fluid interfacing on one side of the device layer. A multilayer metal interconnect structure is disposed on the opposite side of the device layer. This structure places the heating elements in proximity to the fluid gates enabling localized heating, precision heating, and multiplexed temperature control for multiplexed bio-sensing applications.
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公开(公告)号：US09709524B2
公开(公告)日：2017-07-18
申请号：US14713543
申请日：2015-05-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Shao Liu , Jui-Cheng Huang , Tung-Tsun Chen
IPC: H01L23/58 , G01N27/414 , H01L27/085 , H01L23/34 , H01L27/02
CPC classification number: G01N27/4148 , G01N27/4145 , H01L23/345 , H01L27/0211 , H01L27/085 , H01L27/16
Abstract: A device layer of an integrated circuit device includes a semiconductor active layer spanning a plurality of device regions. Each of the device regions has a heating element, a temperature sensor, and bioFETs in the device layer. The bioFETs have source/drain regions and channel regions in the semiconductor active layer and fluid gates exposed on a surface for fluid interfacing on one side of the device layer. A multilayer metal interconnect structure is disposed on the opposite side of the device layer. This structure places the heating elements in proximity to the fluid gates enabling localized heating, precision heating, and multiplexed temperature control for multiplexed bio-sensing applications.
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公开(公告)号：US11099152B2
公开(公告)日：2021-08-24
申请号：US16679015
申请日：2019-11-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Shao Liu , Chun-Ren Cheng , Ching-Ray Chen , Yi-Hsien Chang , Fei-Lung Lai , Chun-Wen Cheng
IPC: H01L27/088 , G01N27/414 , H01L29/66 , H01L21/311
Abstract: The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer.
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公开(公告)号：US10520467B2
公开(公告)日：2019-12-31
申请号：US15912174
申请日：2018-03-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Alexander Kalnitsky , Yi-Shao Liu , Kai-Chih Liang , Chia-Hua Chu , Chun-Ren Cheng , Chun-Wen Cheng
IPC: G01N27/414 , H01L51/05 , H01L51/00 , H01L21/84 , H01L27/12
Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.
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