公开(公告)号：US10823696B2

公开(公告)日：2020-11-03

申请号：US16021077

申请日：2018-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Wen Cheng ,  Yi-Shao Liu ,  Fei-Lung Lai

IPC: G01N27/414 ,  H01L29/66 ,  H01L23/34 ,  H01L29/78 ,  H01L21/84

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure, an isolation layer, an interface layer in an opening of the isolation layer, and a metal crown structure over the interface layer. The interface layer and the metal crown structure are disposed on opposite side of the transistor from a gate structure.

公开(公告)号：US10473616B2

公开(公告)日：2019-11-12

申请号：US15649963

申请日：2017-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shao Liu ,  Chun-Ren Cheng ,  Ching-Ray Chen ,  Yi-Hsien Chang ,  Fei-Lung Lai ,  Chun-Wen Cheng

IPC: G01N27/414 ,  H01L29/66 ,  H01L21/311

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer.

公开(公告)号：US09910009B2

公开(公告)日：2018-03-06

申请号：US15661798

申请日：2017-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alexander Kalnitsky ,  Yi-Shao Liu ,  Kai-Chih Liang ,  Chia-Hua Chu ,  Chun-Ren Cheng ,  Chun-Wen Cheng

IPC: H01L51/05 ,  G01N27/414 ,  H01L27/12 ,  H01L21/84 ,  H01L51/00

CPC classification number: G01N27/4145 ,  G01N27/414 ,  G01N27/4148 ,  H01L21/84 ,  H01L27/1203 ,  H01L51/0093

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

公开(公告)号：US12216077B2

公开(公告)日：2025-02-04

申请号：US17087112

申请日：2020-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wen Cheng ,  Yi-Shao Liu ,  Fei-Lung Lai

IPC: H01L29/78 ,  G01N27/414 ,  H01L23/34 ,  H01L29/66 ,  H01L21/84

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure, an isolation layer, an interface layer in an opening of the isolation layer, and a metal crown structure over the interface layer. The interface layer and the metal crown structure are disposed on opposite side of the transistor from a gate structure.

公开(公告)号：US11828722B2

公开(公告)日：2023-11-28

申请号：US16716196

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chuan Liao ,  Chien-Kuo Yang ,  Yi-Shao Liu ,  Tung-Tsun Chen ,  Chan-Ching Lin ,  Jui-Cheng Huang ,  Felix Ying-Kit Tsui ,  Jing-Hwang Yang

IPC: G01N27/414

CPC classification number: G01N27/4145

Abstract: A biological device includes a substrate, a gate electrode, and a sensing well. The substrate includes a source region, a drain region, a channel region, a body region, and a sensing region. The channel region is disposed between the source region and the drain region. The sensing region is at least disposed between the channel region and the body region. The gate electrode is at least disposed on or above the channel region of the substrate. The sensing well is at least disposed adjacent to the sensing region.

公开(公告)号：US11486854B2

公开(公告)日：2022-11-01

申请号：US16727738

申请日：2019-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alexander Kalnitsky ,  Yi-Shao Liu ,  Kai-Chih Liang ,  Chia-Hua Chu ,  Chun-Ren Cheng ,  Chun-Wen Cheng

IPC: G01N27/414 ,  H01L27/12 ,  H01L29/78 ,  H01L51/00 ,  H01L21/84 ,  H01L29/66 ,  C12Q1/00

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

公开(公告)号：US10393695B2

公开(公告)日：2019-08-27

申请号：US16165748

申请日：2018-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shao Liu ,  Jui-Cheng Huang ,  Tung-Tsun Chen

IPC: H01L21/00 ,  G01N27/414 ,  H01L23/34 ,  H01L27/085 ,  H01L27/16 ,  H01L27/02

Abstract: A method of manufacturing an integrated circuit device includes providing a substrate comprising a semiconductor active layer, and forming source/drain regions, temperature sensors, and heating elements either in the semiconductor active layer or on the front side of the semiconductor active layer. The semiconductor active layer has channel regions between adjacent source/drain regions, and each of the heating elements is aligned over at least a portion of a corresponding temperature sensor. The method also includes forming a metal interconnect structure over the front side of the semiconductor active layer and exposing the channel regions from the back side of the semiconductor active layer substrate. A fluid gate dielectric layer is formed over the exposed channel regions.

公开(公告)号：US09968927B2

公开(公告)日：2018-05-15

申请号：US14719991

申请日：2015-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shao Liu ,  Emerson Cheng ,  Yi-Hsien Chang ,  Chun-Ren Cheng ,  Ching-Ray Chen ,  Alex Kalnitsky ,  Allen Timothy Chang

IPC: H01L27/12 ,  G01N27/414 ,  G01N21/64 ,  B01L3/00

CPC classification number: B01L3/50 ,  B01L3/502715 ,  B01L2300/0636 ,  B01L2300/0645 ,  B01L2300/0654 ,  B01L2300/0816 ,  B01L2300/0887 ,  B01L2300/168 ,  B01L2300/1827 ,  B01L2400/0424 ,  G01N21/6428 ,  G01N21/6454 ,  G01N21/648 ,  G01N27/414 ,  G01N2021/6482 ,  H01L27/1203 ,  H01L27/1211

Abstract: The present disclosure relates to an integrated chip having an integrated optical bio-sensor, and an associated method of fabrication. In some embodiments, the integrated optical bio-sensor has a sensing device arranged within a semiconductor substrate. An optical waveguide structure is located over a first side of the semiconductor substrate at a position over the sensing device. A dielectric structure is disposed onto the optical waveguide structure at a position that separates the optical waveguide structure from a sample retention area configured to receive a sample solution.

公开(公告)号：US20170065958A1

公开(公告)日：2017-03-09

申请号：US15355273

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wen Cheng ,  Jung-Huei Peng ,  Yi-Shao Liu ,  Fei-Lung Lai ,  Shang-Ying Tsai

IPC: B01J19/00 ,  G01R31/28 ,  G01N27/414 ,  G01R1/067 ,  B05D5/04 ,  B05D1/18

CPC classification number: B05C11/1039 ,  B01J19/0046 ,  B01J2219/00286 ,  B01J2219/00353 ,  B01J2219/00387 ,  B01J2219/00418 ,  B01J2219/0043 ,  B01J2219/00596 ,  B01J2219/00605 ,  B01J2219/00623 ,  B01J2219/00659 ,  B01J2219/00698 ,  B05D1/18 ,  B05D5/04 ,  G01N27/4145 ,  G01R1/06783 ,  G01R31/2886 ,  G01R31/2887 ,  G01R31/2889

Abstract: The present disclosure relates to a method of depositing a fluid onto a substrate. In some embodiments, the method may be performed by mounting a substrate to a micro-fluidic probe card, so that the substrate abuts a cavity within the micro-fluidic probe card that is in communication with a fluid inlet and a fluid outlet. A first fluidic chemical is selectively introduced into the cavity via the fluid inlet of the micro-fluidic probe card.

Abstract translation: 本公开涉及一种将流体沉积到基底上的方法。 在一些实施例中，可以通过将衬底安装到微流体探针卡来执行该方法，使得衬底抵靠与流体入口和流体出口连通的微流体探针卡内的空腔。 通过微流体探针卡的流体入口将第一流体化学物质选择性地引入空腔。

公开(公告)号：US09121820B2

公开(公告)日：2015-09-01

申请号：US13974095

申请日：2013-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shao Liu ,  Fei-Lung Lai ,  Chun-Wen Cheng

IPC: H01L29/66 ,  G01N27/414 ,  H01L29/775

CPC classification number: G01N27/4145 ,  H01L29/66439 ,  H01L29/775

Abstract: The present disclosure relates to a top-down method of forming a nanowire structure extending between source and drain regions of a nanowire transistor device, and an associated apparatus. In some embodiments, the method provides a substrate having a device layer disposed over a first dielectric layer. The device layer has a source region and a drain region separated by a device material. The first dielectric layer has an embedded gate structure abutting the device layer. One or more masking layers are selectively formed over the device layer to define a nanowire structure. The device layer is then selectively etched according to the one or more masking layers to form a nanowire structure at a position between the source region and the drain region. By forming the nanowire structure through a masking and etch process, the nanowire structure is automatically connected to the source and drain regions.

Abstract translation: 本发明涉及形成在纳米线晶体管器件的源极和漏极区域之间延伸的纳米线结构的自顶向下的方法，以及相关联的器件。 在一些实施例中，该方法提供了具有设置在第一介电层上的器件层的衬底。 器件层具有由器件材料分离的源极区域和漏极区域。 第一电介质层具有邻接器件层的嵌入式栅极结构。 选择性地在器件层上形成一个或多个掩模层以限定纳米线结构。 然后根据一个或多个掩模层选择性地蚀刻器件层，以在源极区域和漏极区域之间的位置处形成纳米线结构。 通过掩模和蚀刻工艺形成纳米线结构，纳米线结构自动连接到源区和漏区。