公开(公告)号：US20210399054A1

公开(公告)日：2021-12-23

申请号：US16908896

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Jung-Piao Chiu ,  Tzu-Chiang Chen ,  Yu-Sheng Chen

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.

公开(公告)号：US20210375989A1

公开(公告)日：2021-12-02

申请号：US16885231

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Jung-Piao Chiu ,  Tzu-Chiang Chen ,  Yu-Sheng Chen ,  Xinyu BAO

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory device includes a memory cell, a selector layer and a first work function metal layer. The selector layer is disposed between a first electrode and a second electrode over the memory cell. The first work function metal layer is disposed between the selector layer and the first electrode.

公开(公告)号：US20210366819A1

公开(公告)日：2021-11-25

申请号：US16881005

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Jin Cai ,  Yu-Sheng Chen

IPC: H01L23/50 ,  H01L23/44 ,  H01L21/82

Abstract: Cryogenic integrated circuits are provided. A cryogenic integrated circuit includes a thermally conductive base, a data processer, a storage device, a buffer device, a thermally conductive shield and a cooling pipe. The data processer is located on the thermally conductive base. The storage device is located on the thermally conductive base and disposed aside and electrically connected to the data processer. The buffer device is disposed on the data processer. The thermally conductive shield covers the data processer, the storage device and the buffer device. The cooling pipe is located in physical contact with the thermally conductive base and disposed at least corresponding to the data processer.

公开(公告)号：US11482571B2

公开(公告)日：2022-10-25

申请号：US16908896

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Jung-Piao Chiu ,  Tzu-Chiang Chen ,  Yu-Sheng Chen

IPC: H01L23/538 ,  H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.

公开(公告)号：US11380369B2

公开(公告)日：2022-07-05

申请号：US16427292

申请日：2019-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Yu-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen

IPC: H01L27/11592 ,  G11C5/06 ,  H01L27/1159 ,  G11C11/22 ,  H01L45/00 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/24 ,  H01L27/22 ,  H01L27/11597 ,  G11C11/16

Abstract: A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.

公开(公告)号：US20210066590A1

公开(公告)日：2021-03-04

申请号：US17081159

申请日：2020-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chao Lin ,  Jui-Ming Chen ,  Shao-Ming Yu ,  Tung Ying Lee ,  Yu-Sheng Chen

IPC: H01L45/00 ,  H01L27/24

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip that includes depositing a phase change material layer over a bottom electrode. The phase change material is configured to change its degree of crystallinity upon temperature changes. A top electrode layer is deposited over the phase change material layer, and a hard mask layer is deposited over the top electrode layer. The top electrode layer and the hard mask layer are patterned to remove outer portions of the top electrode layer and to expose outer portions of the phase change material layer. An isotropic etch is performed to remove portions of the phase change material layer that are uncovered by the top electrode layer and the hard mask layer. The isotropic etch removes the portions of the phase change material layer faster than portions of the top electrode layer and the hard mask layer.

公开(公告)号：US20210043254A1

公开(公告)日：2021-02-11

申请号：US17078910

申请日：2020-10-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jau-Yi Wu ,  Yu-Sheng Chen

IPC: G11C13/00

Abstract: A method, includes: applying a read voltage at a first read voltage level to read a memory cell for detecting a resistance level of the memory cell; applying the read voltage at a second read voltage level, different from the first read voltage level, to read the memory cell for determining a waveform type has been utilized to program the memory cell; recognizing data bits stored in the memory cell. The data bits stored in the memory cell comprise a first data bit and at least one second data bit. The first data bit is recognized according to the waveform type and is irrelevant with the resistance level. The at least one second data bit is recognized according to the resistance level and is irrelevant with the waveform type. A device is also disclosed herein.

公开(公告)号：US11342380B2

公开(公告)日：2022-05-24

申请号：US16885231

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Jung-Piao Chiu ,  Tzu-Chiang Chen ,  Yu-Sheng Chen ,  Xinyu Bao

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory device includes a memory cell, a selector layer and a first work function metal layer. The selector layer is disposed between a first electrode and a second electrode over the memory cell. The first work function metal layer is disposed between the selector layer and the first electrode.

公开(公告)号：US11276464B2

公开(公告)日：2022-03-15

申请号：US17078910

申请日：2020-10-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jau-Yi Wu ,  Yu-Sheng Chen

IPC: G11C11/00 ,  G11C13/00

Abstract: A method, includes: applying a read voltage at a first read voltage level to read a memory cell for detecting a resistance level of the memory cell; applying the read voltage at a second read voltage level, different from the first read voltage level, to read the memory cell for determining a waveform type has been utilized to program the memory cell; recognizing data bits stored in the memory cell. The data bits stored in the memory cell comprise a first data bit and at least one second data bit. The first data bit is recognized according to the waveform type and is irrelevant with the resistance level. The at least one second data bit is recognized according to the resistance level and is irrelevant with the waveform type. A device is also disclosed herein.

公开(公告)号：US20220059580A1

公开(公告)日：2022-02-24

申请号：US17000582

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Jung-Piao Chiu ,  Tzu-Chiang Chen ,  Yu-Sheng Chen

IPC: H01L27/146 ,  H01L45/00

Abstract: Disclosed herein, in some embodiments, is a memory device. The memory device includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. An upper surface of the bottom electrode faces away from the substrate. A bottom surface of the top electrode faces the substrate. A data storage layer is arranged between the bottom electrode and the top electrode. At least a portion of the bottom surface of the top electrode does not overlap with any portion of the top surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode. Furthermore, at least a portion of the top surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction.