公开(公告)号：US20190195943A1

公开(公告)日：2019-06-27

申请号：US16291793

申请日：2019-03-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Zeng KANG ,  Chih-Hsien CHANG ,  Wen-Shen CHOU ,  Yung-Chow PENG

IPC: G01R31/28 ,  H03K19/20 ,  H03K3/03

CPC classification number: G01R31/2874 ,  G01R31/2855 ,  G01R31/2858 ,  H03K3/0315 ,  H03K19/20

Abstract: An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.

公开(公告)号：US20180152187A1

公开(公告)日：2018-05-31

申请号：US15794331

申请日：2017-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tao YANG ,  Wen-Shen CHOU ,  Yung-Chow PENG

IPC: H03K19/017 ,  H03K19/0185 ,  H01L29/06 ,  H01L27/02 ,  H01L27/092

CPC classification number: H03K19/01721 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/0619 ,  H03K19/018521

Abstract: A level shifter circuit includes a latch module with a first plurality of PMOS transistors and a second plurality of NMOS transistors; a MOS module with a third plurality of MOS transistors operatively connected to the latch module; a fourth plurality of transistors operatively connected between the MOS module and the ground; and a fifth plurality of capacitors operatively connected between the latch module and the gates of fourth plurality of transistors.

公开(公告)号：US20210305248A1

公开(公告)日：2021-09-30

申请号：US17030122

申请日：2020-09-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Hsiang WANG ,  Szu-Lin LIU ,  Jaw-Juinn HORNG ,  Yung-Chow PENG

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/64 ,  H03K17/687

Abstract: A method of biasing a guard ring structure includes biasing a gate of a MOS transistor to a first bias voltage level, biasing first and second S/D regions of the MOS transistor to a power domain voltage level, biasing a gate of the guard ring structure to a second bias voltage level, and biasing first and second heavily doped regions of the guard ring structure to the power domain voltage level. Each of the first and second S/D regions has a first doping type, each of the first and second heavily doped regions has a second doping type different from the first doping type, and each of the first and second S/D regions and the first and second heavily doped regions is positioned in a substrate region having the second doping type.

公开(公告)号：US20210257444A1

公开(公告)日：2021-08-19

申请号：US17306796

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yi CHEN ,  Chung-Chieh YANG ,  Yung-Chow PENG

IPC: H01L49/02 ,  H01L23/522

Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.

公开(公告)号：US20200083134A1

公开(公告)日：2020-03-12

申请号：US16681687

申请日：2019-11-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chieh YANG ,  Yung-Chow PENG ,  Chung-Peng HSIEH ,  Sa-Lly LIU

IPC: H01L23/34 ,  H01L49/02 ,  H01L23/522 ,  H01L23/552 ,  H01L23/64

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact.

公开(公告)号：US20150110158A1

公开(公告)日：2015-04-23

申请号：US14055909

申请日：2013-10-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Szu-Lin LIU ,  Jaw-Juinn HORNG ,  Yung-Chow PENG

IPC: G01K7/34

CPC classification number: G01K7/21 ,  G01K7/20

Abstract: A circuit includes sensing circuitry including at least one sensing element configured to output at least one temperature-dependent voltage. A compare circuit is configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage. A control circuit is configured to generate at least one control signal in response to the intermediate voltage. A switching circuit is configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal having a pulse width that is based on a temperature sensed by the sensing circuitry.

Abstract translation: 电路包括感测电路，其包括被配置为输出至少一个温度相关电压的至少一个感测元件。 响应于将至少一个依赖于温度的电压与反馈电压进行比较，比较电路被配置为产生至少一个中间电压。 控制电路被配置为响应于中间电压产生至少一个控制信号。 开关电路被配置为响应于所述至少一个控制信号将耦合到反馈节点的电容器耦合到第一电压源和第二电压源中的一个，以产生具有基于温度的脉冲宽度的输出信号 由感测电路感测。

公开(公告)号：US20140215419A1

公开(公告)日：2014-07-31

申请号：US13751195

申请日：2013-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Amit KUNDU ,  Jaw-Juinn HORNG ,  Yung-Chow PENG ,  Shih-Cheng YANG ,  Chung-Kai LIN

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5072 ,  G06F2217/10 ,  G06F2217/78 ,  H01L27/0207

Abstract: A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom.

公开(公告)号：US20230343785A1

公开(公告)日：2023-10-26

申请号：US18343447

申请日：2023-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Hsiang WANG ,  Szu-Lin LIU ,  Jaw-Juinn HORNG ,  Yung-Chow PENG

IPC: H01L27/092 ,  H01L21/8238 ,  H03K17/687 ,  H01L23/64 ,  H01L27/02

CPC classification number: H01L27/0921 ,  H01L21/823814 ,  H03K17/6872 ,  H01L23/642 ,  H01L21/823871 ,  H01L27/0222

Abstract: A method of manufacturing an integrated circuit (IC) device includes forming a metal oxide semiconductor (MOS) transistor including a first gate and first and second source/drain (S/D) regions, the first and second S/D regions having a first doping type and being formed in a substrate region having a second doping type different from the first doping type, forming a guard ring structure surrounding the MOS transistor, the guard ring structure including a second gate and first and second heavily doped regions, the first and second heavily doped regions being formed in the substrate region and having the second doping type, and constructing a first electrical connection between the first and second gates.

公开(公告)号：US20210125890A1

公开(公告)日：2021-04-29

申请号：US17140645

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chieh YANG ,  Yung-Chow PENG ,  Chung-Peng HSIEH ,  Sa-Lly LIU

IPC: H01L23/34 ,  H01L23/64 ,  H01L23/552 ,  H01L23/522 ,  H01L49/02

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact.

公开(公告)号：US20200279809A1

公开(公告)日：2020-09-03

申请号：US16796668

申请日：2020-02-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Zeng KANG ,  Wen-Shen CHOU ,  Yung-Chow PENG

IPC: H01L23/522 ,  H01L27/06 ,  H01L23/535 ,  H01L49/02 ,  H01L21/768

Abstract: A semiconductor device includes transistors and a resistor. The transistors are connected in series between a power terminal and a ground terminal, and gate terminals of the transistors being connected together. The resistor is overlaid above the transistors. The resistor is connected between a source terminal of the transistors and the ground terminal.