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    GENERATION OF LAYOUT INCLUDING POWER DELIVERY NETWORK
    2.
    发明申请
    GENERATION OF LAYOUT INCLUDING POWER DELIVERY NETWORK 有权

    公开(公告)号：US20220215152A1

    公开(公告)日：2022-07-07

    申请号：US17703898

    申请日：2022-03-24

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chung-Chieh YANG ,  Tai-Yi CHEN ,  Yun-Ru CHEN ,  Yung-Chow PENG

    IPC: G06F30/398 ,  G06F30/392 ,  G06F30/367 ,  G06F30/3953

    Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; and adding at least one additional conductive pillar or at least one additional power rail in the initial power delivery network according to a relationship of a pillar density of the initial power delivery network and a maximum pillar density when the circuit design does not meet the predetermined specification.

    CIRCUITS AND METHODS FOR REDUCING KICKBACK NOISE IN A COMPARATOR
    4.
    发明申请
    CIRCUITS AND METHODS FOR REDUCING KICKBACK NOISE IN A COMPARATOR 有权

    公开(公告)号：US20210044281A1

    公开(公告)日：2021-02-11

    申请号：US17080317

    申请日：2020-10-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

    Inventor： Chin-Ho CHANG ,  Jaw-Juinn HORNG ,  Yung-Chow PENG

    IPC: H03K3/013 ,  H03K3/023

    Abstract: Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

    3D THERMAL DETECTION CIRCUITS AND METHODS
    6.
    发明申请
    3D THERMAL DETECTION CIRCUITS AND METHODS 审中-公开

    公开(公告)号：US20170184459A1

    公开(公告)日：2017-06-29

    申请号：US15460098

    申请日：2017-03-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Szu-Lin LIU ,  Jaw-Juinn HORNG ,  Yung-Chow PENG

    IPC: G01K7/21

    CPC classification number: G01K7/21 ,  G01K7/20

    Abstract: A three-dimensional integrated circuit includes a first layer including at least one sensing element configured to output at least one temperature-dependent voltage; and a second layer disposed vertically with respect to the first layer and coupled to the first layer by at least one via. The second layer includes: a compare circuit configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage; a control circuit configured to generate at least one control signal in response to the intermediate voltage; and a switching circuit configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal that is based on a temperature sensed by the sensing element.

    CASCODE CMOS STRUCTURE
    7.
    发明申请
    CASCODE CMOS STRUCTURE 审中-公开
    CASCODE CMOS结构

    公开(公告)号：US20150020039A1

    公开(公告)日：2015-01-15

    申请号：US14464730

    申请日：2014-08-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Fu-Lung HSUEH ,  Chih-Ping CHAO ,  Chewn-Pu JOU ,  Yung-Chow PENG ,  Harry-Hak-Lay CHUANG ,  Kuo-Tung SUNG

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F17/50 ,  G06F17/5009 ,  H01L27/088 ,  H01L27/0922

    Abstract: A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.

    Abstract translation: MOS器件包括具有第一和第二触点的有源区。 第一和第二栅极设置在第一和第二触点之间。 第一门被设置成与第一接触相邻并且具有第三接触。 第二栅极被设置成与第二触点相邻并且具有耦合到第三触点的第四触点。 由有源区和第一栅极限定的晶体管具有第一阈值电压，并且由有源区和第二栅极限定的晶体管具有第二阈值电压。

    CIRCUITS AND METHODS FOR REDUCING KICKBACK NOISE IN A COMPARATOR
    8.
    发明申请
    CIRCUITS AND METHODS FOR REDUCING KICKBACK NOISE IN A COMPARATOR 有权

    公开(公告)号：US20220302903A1

    公开(公告)日：2022-09-22

    申请号：US17837960

    申请日：2022-06-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Ho CHANG ,  Jaw-Juinn HORING ,  Yung-Chow PENG

    IPC: H03K3/013 ,  H03K3/023

    Abstract: Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

    CAPACITOR STRUCTURE WITH LOW CAPACITANCE
    10.
    发明申请
    CAPACITOR STRUCTURE WITH LOW CAPACITANCE 审中-公开

    公开(公告)号：US20200044012A1

    公开(公告)日：2020-02-06

    申请号：US16216889

    申请日：2018-12-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tai-Yi CHEN ,  Chung-Chieh YANG ,  Yung-Chow PENG

    IPC: H01L49/02 ,  H01L23/522

    Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.

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