公开(公告)号：US20210201999A1

公开(公告)日：2021-07-01

申请号：US17186539

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Chien-Chen Lin

IPC: G11C15/04 ,  H01L27/02

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

公开(公告)号：US10714181B2

公开(公告)日：2020-07-14

申请号：US15799253

申请日：2017-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Chien-Chen Lin

IPC: G11C15/00 ,  G11C15/04 ,  H01L27/02 ,  G11C11/412

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

公开(公告)号：US11176997B2

公开(公告)日：2021-11-16

申请号：US17186539

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Chien-Chen Lin

IPC: G11C15/00 ,  G11C15/04 ,  H01L27/02 ,  G11C11/412

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

公开(公告)号：US20190004718A1

公开(公告)日：2019-01-03

申请号：US15938502

申请日：2018-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hao HSU ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Chiting Cheng ,  Fu-An Wu ,  Hung-Jen Liao ,  Jung-Ping Yang ,  Jonathan Tsung-Yung Chang ,  Wei Min Chan ,  Yen-Huei Chen ,  Yangsyu Lin ,  Chien-Chen Lin

IPC: G06F3/06 ,  G11C11/4074 ,  G11C16/12 ,  G11C16/30 ,  G11C5/14

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to control minimize power consumption.

公开(公告)号：US20180069711A1

公开(公告)日：2018-03-08

申请号：US15259948

申请日：2016-09-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus LU ,  Wei-Min Chan ,  Chien-Chen Lin

IPC: H04L9/32 ,  G11C11/417 ,  G06F12/14

CPC classification number: H04L9/3278 ,  G06F12/1408 ,  G06F2212/1052 ,  G06F2212/402 ,  G11C7/20 ,  G11C8/12 ,  G11C11/417 ,  G11C2029/4402 ,  H04L9/0866 ,  H04L9/3247

Abstract: A memory device includes a memory block comprises a plurality of bits, wherein at least a first bit of the plurality of bits presents an initial logic state each time it is powered on; a start-up circuit configured to power on and off the memory block N times, where N is an odd integer greater than 1, and wherein the at least first bit presents an initial state after each respective power cycle of the memory block; and an authentication circuit, coupled to the memory block, and comprising an election engine that is configured to elect an initial state that occurs (N+1)/2 or more times after N power cycles that are performed by the start-up circuit, as a majority initial logic state for the first bit.