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    Semiconductor memory with respective power voltages for memory cells
    1.
    发明授权
    Semiconductor memory with respective power voltages for memory cells 有权

    公开(公告)号：US11264088B2

    公开(公告)日：2022-03-01

    申请号：US16997857

    申请日：2020-08-19

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Cheng Wu ,  Chih-Yu Lin ,  Kao-Cheng Lin ,  Wei-Min Chan ,  Yen-Huei Chen

    IPC: G11C11/419 ,  G11C11/413 ,  H01L27/11 ,  G11C11/412

    Abstract: A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit is configured to provide a first power voltage via a conductive line for the plurality of first memory cells, and to provide a second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or smaller than the first power voltage and the second power voltage, for corresponding memory cells of the plurality of first memory cells via the conductive line and for corresponding memory cells of the plurality of second memory cells. A circuit structure of the power circuit is different from a circuit structure of the header circuit.

    SRAM-based authentication circuit
    7.
    发明授权
    SRAM-based authentication circuit 有权

    公开(公告)号：US11012246B2

    公开(公告)日：2021-05-18

    申请号：US15259948

    申请日：2016-09-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Lien Linus Lu ,  Wei-Min Chan ,  Chien-Chen Lin

    IPC: H04L9/32 ,  G11C7/20 ,  G11C8/12 ,  H04L9/08 ,  G06F12/14 ,  G11C11/417 ,  G11C29/14 ,  G11C16/34 ,  G11C29/44

    Abstract: A memory device includes a memory block comprises a plurality of bits, wherein at least a first bit of the plurality of bits presents an initial logic state each time it is powered on; a start-up circuit configured to power on and off the memory block N times, where N is an odd integer greater than 1, and wherein the at least first bit presents an initial state after each respective power cycle of the memory block; and an authentication circuit, coupled to the memory block, and comprising an election engine that is configured to elect an initial state that occurs (N+1)/2 or more times after N power cycles that are performed by the start-up circuit, as a majority initial logic state for the first bit.

    SRAM-based authentication circuit
    8.
    发明授权
    SRAM-based authentication circuit 有权

    公开(公告)号：US10439827B2

    公开(公告)日：2019-10-08

    申请号：US15288382

    申请日：2016-10-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chien-Chen Lin ,  Shih-Lien Linus Lu ,  Wei-Min Chan

    IPC: G11C11/419 ,  H04L9/32 ,  G06F12/14 ,  G06F21/44 ,  G06F21/73

    Abstract: A memory device includes a memory block that includes a plurality of memory bits, wherein each bit is configured to present a first logical state; and an authentication circuit, coupled to the plurality of memory bits, wherein the authentication circuit is configured to access a first bit under either a reduced read margin or a reduced write margin condition to determine a stability of the first bit by detecting whether the first logical state flips to a second logical state, and based on the determined stability of at least the first bit, to generate a physically unclonable function (PUF) signature.

    SRAM cell word line structure with reduced RC effects
    9.
    发明授权
    SRAM cell word line structure with reduced RC effects 有权

    公开(公告)号：US12245412B2

    公开(公告)日：2025-03-04

    申请号：US18362786

    申请日：2023-07-31

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Hidehiro Fujiwara ,  Wei-Min Chan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Hung-Jen Liao

    IPC: H10B10/00 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02

    Abstract: A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.

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