公开(公告)号：US09318190B1

公开(公告)日：2016-04-19

申请号：US14501623

申请日：2014-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Kuei Lin ,  Hung-Jen Liao ,  Yen-Huei Chen

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C7/14

Abstract: An electronic device is disclosed that includes n memory cells, a replica memory array, and a sensing unit. Each of the n memory cells stores bit data, in which n is a positive integer. The replica memory array includes a first reference memory cell having a high logic state, a second reference memory cell having a low logic state, n−1 first pseudo reference memory cells having the low logic state, and n−1 second pseudo reference memory cells having the high logic state. The first reference memory cell and the n−1 first pseudo reference memory cells generate a first signal, and the second reference memory cell and the n−1 second pseudo reference memory cells generate a second signal. The sensing unit determines a logic state of the bit data of one of the n memory cells according to the first signal and the second signal.

Abstract translation: 公开了一种包括n个存储单元，复制存储器阵列和感测单元的电子设备。 n个存储单元中的每一个存储位数据，其中n是正整数。 复制存储器阵列包括具有高逻辑状态的第一参考存储单元，具有低逻辑状态的第二参考存储单元，具有低逻辑状态的n-1个第一伪参考存储器单元和n-1个第二伪参考存储器单元 具有高逻辑状态。 第一参考存储单元和n-1个第一伪参考存储单元产生第一信号，第二参考存储单元和第n-1个第二伪参考存储单元产生第二信号。 感测单元根据第一信号和第二信号确定n个存储器单元之一的位数据的逻辑状态。

公开(公告)号：US20140133219A1

公开(公告)日：2014-05-15

申请号：US13674192

申请日：2012-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Wei-Cheng Wu ,  Wei Min Chan ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: G11C5/14 ,  G11C11/419

CPC classification number: G11C11/419

Abstract: Some embodiments of the present disclosure relate to a memory array having a cell voltage generator configured to provide a cell voltage header to a plurality of memory cells. The cell voltage generator is connected to the memory cells by way of supply voltage line and controls a supply voltage of the memory cells. The cell voltage generator has a pull-down element coupled between a control node of the supply voltage line and a ground terminal, and a one or more pull-up elements connected in parallel between the control node and a cell voltage source. A control unit is configured to provide one or more variable valued pull-up enable signals to input nodes of the pull-up elements. The variable valued pull-up enable signals operate the pull-up elements to selectively connect the supply voltage line from the cell voltage source to provide a cell voltage header with a high slew rate.

Abstract translation: 本公开的一些实施例涉及具有单元电压发生器的存储器阵列，其被配置为向多个存储器单元提供单元电压报头。 电池电压发生器通过电源电压线连接到存储器单元，并控制存储器单元的电源电压。 电池电压发生器具有耦合在电源电压线的控制节点和接地端子之间的下拉元件以及在控制节点和电池电压源之间并联连接的一个或多个上拉元件。 控制单元被配置为向上拉元件的输入节点提供一个或多个可变值上拉使能信号。 可变值上拉使能信号操作上拉元件以选择性地将电源电压线与电池电压源连接，以提供具有高压摆率的电池电压头。

公开(公告)号：US20210201999A1

公开(公告)日：2021-07-01

申请号：US17186539

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Chien-Chen Lin

IPC: G11C15/04 ,  H01L27/02

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

公开(公告)号：US10714181B2

公开(公告)日：2020-07-14

申请号：US15799253

申请日：2017-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Chien-Chen Lin

IPC: G11C15/00 ,  G11C15/04 ,  H01L27/02 ,  G11C11/412

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

公开(公告)号：US10541007B2

公开(公告)日：2020-01-21

申请号：US16265886

申请日：2019-02-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jonathan Tsung-Yung Chang ,  Cheng-Hung Lee ,  Chi-Ting Cheng ,  Hung-Jen Liao ,  Jhon-Jhy Liaw ,  Yen-Huei Chen

IPC: G11C5/02 ,  G11C5/14 ,  G11C7/10 ,  G11C7/12 ,  G11C11/417 ,  G11C7/22

Abstract: A device includes a memory array. The memory array includes a first sub-bank, a second sub-bank, a strap cell and a continuous data line. The strap cell is arranged between the first sub-bank and the second sub-bank. The continuous data line includes a first portion coupled to the first sub-bank and a second portion disposed across the second sub-bank. The first portion of the continuous data line and the second portion of the continuous data line are disposed at separate layers above the strap cell.

公开(公告)号：US10510403B2

公开(公告)日：2019-12-17

申请号：US16211589

申请日：2018-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mahmut Sinangil ,  Hidehiro Fujiwara ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yen-Huei Chen ,  Sahil Preet Singh

IPC: G11C11/00 ,  G11C11/419 ,  G11C8/12 ,  G11C11/412 ,  G11C7/16 ,  G11C8/16 ,  G11C7/18

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

公开(公告)号：US10510380B2

公开(公告)日：2019-12-17

申请号：US16391986

申请日：2019-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-An Wu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yu-Hao Hsu

IPC: G11C5/14 ,  H03K17/687 ,  H03K17/22

Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.

公开(公告)号：US10411019B2

公开(公告)日：2019-09-10

申请号：US15186446

申请日：2016-06-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hidehiro Fujiwara ,  Wei-Min Chan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: H01L27/11 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528

Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.

公开(公告)号：US20190252008A1

公开(公告)日：2019-08-15

申请号：US16391986

申请日：2019-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-An Wu ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang ,  Yu-Hao Hsu

IPC: G11C5/14 ,  H03K17/22 ,  H03K17/687

Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.

公开(公告)号：US10276231B2

公开(公告)日：2019-04-30

申请号：US15888517

申请日：2018-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Yen-Huei Chen ,  Mahmut Sinangil

IPC: G11C11/412 ,  H01L27/11 ,  G11C11/419 ,  G11C11/418 ,  G11C8/14

Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.