公开(公告)号：US20240257874A1

公开(公告)日：2024-08-01

申请号：US18103350

申请日：2023-01-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Hsien Chen ,  Chun-Yao Ko ,  Liang-Tai Kuo ,  YingKit Felix Tsui

IPC分类号： G11C16/04 ,  G11C16/24 ,  H10B41/10 ,  H10B41/23 ,  H10B41/35 ,  H10B41/70

CPC分类号： G11C16/0483 ,  G11C16/24 ,  H10B41/10 ,  H10B41/23 ,  H10B41/35 ,  H10B41/70

摘要： A memory device includes a first well region, a second well region, and third well regions. The second well region is interposed between the first region and the third well regions, and the third well regions are separated from one another. The memory device includes floating gates disposed over the first to third well regions, wherein each of the floating gates continuously extends from the first well region to a corresponding one of the third well regions. The memory device includes a bit line write region disposed within the second well region. The bit line write region comprises first source/drain regions on opposite sides of each floating gate. The memory device includes a bit line read region disposed within the second well region and spaced from the bit line write region. The bit line read region comprises second source/drain regions on the opposite sides of each floating gate.

公开(公告)号：US10553597B2

公开(公告)日：2020-02-04

申请号：US16231854

申请日：2018-12-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Hsien Chen ,  Liang-Tai Kuo ,  Hau-Yan Lu ,  Chun-Yao Ko

IPC分类号： H01L27/11526 ,  H01L29/49 ,  H01L27/02 ,  H01L23/528 ,  H01L29/10 ,  H01L29/66 ,  H01L27/11558 ,  H01L27/11521 ,  H01L29/94

摘要： A memory cell includes a first transistor coupled to a source line, wherein the first transistor is in a first well. The memory cell further includes a second transistor coupled to the first transistor and a bit line, wherein the second transistor is in the first well. The memory cell further includes a first capacitor coupled to a word line and the second transistor, wherein the first capacitor is in a second well. The memory cell further includes a second capacitor coupled to the second transistor and an erase gate, wherein the second capacitor is in the second well. In some embodiments, the first well contacts the second well on a first side of the first well.

公开(公告)号：US20150132905A1

公开(公告)日：2015-05-14

申请号：US14543082

申请日：2014-11-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ta-Chuan Liao ,  Chien-Kuo Yang ,  Felix Ying-Kit Tsui ,  Shih-Hsien Chen ,  Liang-Tai Kuo ,  Chun-Yao Ko

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L21/265 ,  H01L49/02

CPC分类号： H01L27/1156 ,  H01L21/265 ,  H01L21/28273 ,  H01L27/11558 ,  H01L28/60 ,  H01L29/788 ,  H01L29/7881

摘要： The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode.

摘要翻译： NVM器件包括具有第一区域和第二区域的半导体衬底。 NVM装置包括形成在第一区域中的数据存储结构，并被设计成可操作地保持电荷。 NVM装置包括形成在第二区域中的电容器，并与用于数据操作的数据存储结构耦合。 数据存储结构包括在半导体衬底中的第一类型的第一掺杂阱。 数据存储结构包括第一掺杂阱上的第一栅介质特征。 数据存储结构包括设置在第一栅极电介质特征上并被配置为浮置的第一栅电极。 电容器包括第一类型的第二掺杂阱。 电容器包括第二掺杂阱上的第二栅极电介质特征。 电容器还包括设置在第二栅极电介质特征上并连接到第一栅电极的第二栅电极。