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公开(公告)号：US20220384465A1
公开(公告)日：2022-12-01
申请号：US17331936
申请日：2021-05-27
发明人： Wen-Shun LO , Tai-Yi WU , YingKit Felix Tsui
IPC分类号： H01L27/11524 , H01L27/11529 , H01L29/788 , H01L29/94 , H01L21/266 , H01L27/11531 , H01L29/66
摘要： A memory device includes a substrate, a first transistor, a second transistor, and a capacitor. The first transistor is over the substrate and includes a select gate. The second transistor is over the substrate and connected to the first transistor in series, in which the second transistor includes a floating gate. The capacitor is over the substrate and connected to the second transistor, wherein the capacitor includes a top electrode, a bottom electrode in the substrate, and an insulating layer between the top electrode and the bottom electrode. The insulating layer includes nitrogen. A nitrogen concentration of the insulating layer increases in a direction from the top electrode to the bottom electrode.
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公开(公告)号：US12085751B2
公开(公告)日：2024-09-10
申请号：US17811381
申请日：2022-07-08
CPC分类号： G02B6/122 , G02B6/131 , G02B6/1347 , G02B6/136 , G02B2006/12061 , G02B2006/12126 , G02B2006/12169 , G02B2006/12173 , G02B6/1342
摘要： Some implementations described herein include a photonics integrated circuit device including a photonics structure. The photonics structure includes a waveguide structure and an optical attenuator structure. In some implementation, the optical attenuator structure is formed on an end region of the waveguide structure and includes a metal material or a doped material. In some implementations, the optical attenuator structure includes a gaussian doping profile within a portion of the waveguide structure. The optical attenuator structure may absorb electromagnetic waves at the end of the waveguide structure with an efficiency that is improved relative to a spiral optical attenuator structure or metal cap optical attenuator structure.
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公开(公告)号：US20240257874A1
公开(公告)日：2024-08-01
申请号：US18103350
申请日：2023-01-30
摘要： A memory device includes a first well region, a second well region, and third well regions. The second well region is interposed between the first region and the third well regions, and the third well regions are separated from one another. The memory device includes floating gates disposed over the first to third well regions, wherein each of the floating gates continuously extends from the first well region to a corresponding one of the third well regions. The memory device includes a bit line write region disposed within the second well region. The bit line write region comprises first source/drain regions on opposite sides of each floating gate. The memory device includes a bit line read region disposed within the second well region and spaced from the bit line write region. The bit line read region comprises second source/drain regions on the opposite sides of each floating gate.
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公开(公告)号：US11610907B2
公开(公告)日：2023-03-21
申请号：US17331936
申请日：2021-05-27
发明人： Wen-Shun Lo , Tai-Yi Wu , YingKit Felix Tsui
IPC分类号： H01L27/11524 , H01L27/11529 , H01L29/788 , H01L29/66 , H01L21/266 , H01L27/11531 , H01L29/94
摘要： A memory device includes a substrate, a first transistor, a second transistor, and a capacitor. The first transistor is over the substrate and includes a select gate. The second transistor is over the substrate and connected to the first transistor in series, in which the second transistor includes a floating gate. The capacitor is over the substrate and connected to the second transistor, wherein the capacitor includes a top electrode, a bottom electrode in the substrate, and an insulating layer between the top electrode and the bottom electrode. The insulating layer includes nitrogen. A nitrogen concentration of the insulating layer increases in a direction from the top electrode to the bottom electrode.
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