公开(公告)号：US20220336482A1

公开(公告)日：2022-10-20

申请号：US17854068

申请日：2022-06-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

IPC分类号： H01L27/11524 ,  H01L27/11529 ,  H01L29/66 ,  H01L29/06 ,  H01L29/788 ,  H01L27/11531

摘要： Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region. A second memory active region is disposed within the second well region and is laterally offset from the first memory active region by a non-zero distance

公开(公告)号：US09711516B2

公开(公告)日：2017-07-18

申请号：US14928688

申请日：2015-10-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Shih-Hsien Chen ,  Hau-Yan Lu ,  Liang-Tai Kuo ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

IPC分类号： H01L27/11 ,  H01L27/1156 ,  H01L27/11524 ,  H01L27/11558

CPC分类号： H01L27/1156 ,  G11C16/0433 ,  G11C2216/04 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11558 ,  H01L29/42328 ,  H01L29/7883

摘要： A non-volatile memory structure includes a semiconductor substrate and a first layer of a first dopant type in the semiconductor substrate. The non-volatile memory structure further includes a first well region of a second dopant type over the first layer, a second well region of the second dopant type over the first layer and spaced apart from the first well region, and a third well region of the first dopant type disposed between the first well region and the second well region and extending downward to the first layer.

公开(公告)号：US09620594B2

公开(公告)日：2017-04-11

申请号：US14500425

申请日：2014-09-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Hsien Chen ,  Liang-Tai Kuo ,  Hau-Yan Lu ,  Chun-Yao Ko

IPC分类号： H01L27/108 ,  H01L29/10 ,  H01L29/49 ,  H01L27/02 ,  H01L23/528 ,  H01L27/11558 ,  H01L29/66 ,  H01L29/94

CPC分类号： H01L27/11526 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/1095 ,  H01L29/4916 ,  H01L29/66181 ,  H01L29/66825 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.

公开(公告)号：US20220415914A1

公开(公告)日：2022-12-29

申请号：US17408621

申请日：2021-08-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wen-Shun Lo ,  Tai-Yi Wu ,  Shih-Hsien Chen ,  Ying Kit Felix Tsui

IPC分类号： H01L27/11524 ,  H01L27/11519

摘要： In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a floating gate electrode disposed over the substrate, a contact etch stop layer (CESL) structure disposed over the floating gate electrode, an insulating stack separating the floating gate electrode from the CESL structure, the insulating stack including a first resist protective layer disposed over the floating gate electrode, a second resist protective layer disposed over the first resist protective layer, and an insulating layer separating the first resist protective layer from the second resist protective layer.

公开(公告)号：US10163920B2

公开(公告)日：2018-12-25

申请号：US15465918

申请日：2017-03-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Hsien Chen ,  Liang-Tai Kuo ,  Hau-Yan Lu ,  Chun-Yao Ko

IPC分类号： H01L27/11526 ,  H01L29/49 ,  H01L27/02 ,  H01L23/528 ,  H01L29/10 ,  H01L29/66 ,  H01L27/11558 ,  H01L27/11521 ,  H01L29/94

摘要： A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.

公开(公告)号：US09159741B2

公开(公告)日：2015-10-13

申请号：US14543082

申请日：2014-11-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ta-Chuan Liao ,  Chien-Kuo Yang ,  Felix Ying-Kit Tsui ,  Shih-Hsien Chen ,  Liang-Tai Kuo ,  Chun-Yao Ko

IPC分类号： H01L27/11 ,  H01L27/115 ,  H01L29/788 ,  H01L21/265 ,  H01L21/28 ,  H01L49/02

CPC分类号： H01L27/1156 ,  H01L21/265 ,  H01L21/28273 ,  H01L27/11558 ,  H01L28/60 ,  H01L29/788 ,  H01L29/7881

摘要： The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode.

摘要翻译： NVM器件包括具有第一区域和第二区域的半导体衬底。 NVM装置包括形成在第一区域中的数据存储结构，并被设计成可操作地保持电荷。 NVM装置包括形成在第二区域中的电容器，并与用于数据操作的数据存储结构耦合。 数据存储结构包括在半导体衬底中的第一类型的第一掺杂阱。 数据存储结构包括第一掺杂阱上的第一栅介质特征。 数据存储结构包括设置在第一栅极电介质特征上并被配置为浮置的第一栅电极。 电容器包括第一类型的第二掺杂阱。 电容器包括第二掺杂阱上的第二栅极电介质特征。 电容器还包括设置在第二栅极电介质特征上并连接到第一栅电极的第二栅电极。

公开(公告)号：US20240107755A1

公开(公告)日：2024-03-28

申请号：US18534818

申请日：2023-12-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

IPC分类号： H10B41/35 ,  G11C16/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/788 ,  H10B41/41 ,  H10B41/42

CPC分类号： H10B41/35 ,  G11C16/10 ,  H01L29/0649 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/41 ,  H10B41/42 ,  G11C16/30

摘要： Various embodiments of the present disclosure are directed towards a semiconductor structure including a first well region disposed within a substrate and comprising a first doping type. A conductive structure overlies the first well region. A pair of first doped regions is disposed within the first well region on opposing sides of the conductive structure. The pair of first doped regions comprise a second doping type opposite the first doping type. A pair of second doped regions is disposed within the first well region on the opposing sides of the conductive structure. The pair of second doped regions comprise the second doping type and are laterally offset from the pair of first doped regions by a non-zero distance.

公开(公告)号：US11844213B2

公开(公告)日：2023-12-12

申请号：US17854068

申请日：2022-06-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

IPC分类号： G11C16/00 ,  H10B41/35 ,  H01L29/66 ,  H01L29/06 ,  H01L29/788 ,  G11C16/10 ,  H10B41/41 ,  H10B41/42 ,  G11C16/30

CPC分类号： H10B41/35 ,  G11C16/10 ,  H01L29/0649 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/41 ,  H10B41/42 ,  G11C16/30

摘要： Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region. A second memory active region is disposed within the second well region and is laterally offset from the first memory active region by a non-zero distance.

公开(公告)号：US10784276B2

公开(公告)日：2020-09-22

申请号：US16200023

申请日：2018-11-26

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： Hau-Yan Lu ,  Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

IPC分类号： H01L27/11568 ,  H01L27/11521

摘要： A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.

公开(公告)号：US10141323B2

公开(公告)日：2018-11-27

申请号：US14987452

申请日：2016-01-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Hau-Yan Lu ,  Shih-Hsien Chen ,  Chun-Yao Ko ,  Felix Ying-Kit Tsui

IPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L27/11521

摘要： A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.