公开(公告)号：US06229363B1

公开(公告)日：2001-05-08

申请号：US09224354

申请日：1999-01-04

申请人： Satoshi Eto ,  Masato Matsumiya ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

发明人： Satoshi Eto ,  Masato Matsumiya ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

IPC分类号： H03L708

CPC分类号： G11C7/1057 ,  G06F1/10 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： A semiconductor device having the function of generating an internal clock signal delayed by a predetermined phase by adjusting the phase of an external clock signal, includes a first clock phase circuit for roughly adjusting the phase of the external clock signal; and a second clock phase adjusting circuit for controlling the phase of the internal clock signal with higher accuracy than the first clock phase adjusting circuit. The semiconductor device having such a construction executes phase comparisons by the first and second clock phase adjusting circuits independently of each other, and when a phase control operation by the second clock phase adjusting circuit is made subordinate to that of the first clock phase adjusting circuit, the delay time of each of a plurality of delay elements inside the first clock phase adjusting circuit is set to a value larger than a power source jitter resulting from a noise of a power source and a jitter of the external clock signal.

摘要翻译： 具有通过调整外部时钟信号的相位而产生延迟预定相位的内部时钟信号的功能的半导体器件包括用于大致调整外部时钟信号的相位的第一时钟相位电路; 以及第二时钟相位调整电路，用于以比第一时钟相位调整电路更高的精度来控制内部时钟信号的相位。 具有这种结构的半导体器件执行第一和第二时钟相位调整电路彼此独立的相位比较，并且当第二时钟相位调整电路的相位控制操作从属于第一时钟相位调整电路的相位控制操作时， 第一时钟相位调整电路内的多个延迟元件中的每一个的延迟时间被设定为大于由电源的噪声和外部时钟信号的抖动导致的电源抖动的值。

公开(公告)号：US6115284A

公开(公告)日：2000-09-05

申请号：US317902

申请日：1999-05-25

申请人： Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

发明人： Masato Matsumiya ,  Satoshi Eto ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C7/12 ,  G11C11/407 ,  G11C11/4094 ,  G11C11/24

CPC分类号： G11C11/4094 ,  G11C7/12

摘要： The present invention relates to a memory device including memory cells each formed of a cell transistor connected to bit and word line and a cell capacitor. The memory device includes a pre-charging circuit for pre-charging bit line to a first voltage, a sense amplifier for detecting voltages of bit lines and driving the bit lines to a second voltage for H level or a third voltage for L level, and a word line driving circuit for driving word lines to make the writing voltage for H level of the cell capacitor to a fourth voltage lower than the second voltage. The present invention is characterized in that the first voltage is lower than an intermediate value between the second and third voltages. According to the present invention, it becomes possible to prevent the voltage V.sub.ds of the cell transistor from being zero by setting the writing voltage (fourth voltage) for H level of the cell capacitor to be lower than the voltage for H level (second voltage) of the bit line, thus reducing a time of writing or re-writing data. Additionally, a pre-charge voltage (first voltage) of the bit lines is set to be lower than the half of the amplitude of the bit line. Thereby, it also becomes possible to prevent the very small voltage of the bit line from being smaller according to the lowered H level voltage in the memory cell.

摘要翻译： 本发明涉及包括由连接到位和字线的单元晶体管形成的存储单元和单元电容器的存储器件。 存储装置包括用于将位线预充电到第一电压的预充电电路，用于检测位线的电压并将位线驱动为用于H电平的第二电压或L电平的第三电压的读出放大器，以及 用于驱动字线以使单元电容器的H电平的写入电压低于低于第二电压的第四电压的字线驱动电路。 本发明的特征在于，第一电压低于第二和第三电压之间的中间值。 根据本发明，通过将单元电容器的H电平的写入电压（第四电压）设定为低于H电平（第二电压）的电压，可以防止单元晶体管的电压Vds为零， 的位线，从而减少写入或重写数据的时间。 此外，位线的预充电电压（第一电压）被设置为低于位线的幅度的一半。 因此，根据存储单元中的低电平电平，也可以防止位线的非常小的电压变小。

公开(公告)号：US20100321983A1

公开(公告)日：2010-12-23

申请号：US12718819

申请日：2010-03-05

申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC分类号： G11C11/24 ,  G11C5/14

CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

公开(公告)号：US20100202874A1

公开(公告)日：2010-08-12

申请号：US12671163

申请日：2008-10-02

申请人： Noriyuki Hayashi ,  Yasuaki Jinnai ,  Hiroshi Suzuki ,  Yuki Ishii

发明人： Noriyuki Hayashi ,  Yasuaki Jinnai ,  Hiroshi Suzuki ,  Yuki Ishii

IPC分类号： F01D17/16

CPC分类号： F01D17/165 ,  F05D2220/40 ,  F05D2250/182 ,  F05D2250/19 ,  F05D2260/30 ,  F05D2260/56

摘要： When changing a nozzle blade angle by rotating a drive ring, a contact load generated between an inner circumferential surface of the drive ring and an outer circumferential surface of a mount can be reduced, allowing the drive ring to rotate smoothly and reducing the amount of wear and a driving force. It is also possible to reduce an impact force, such as engine vibrations, generated at the drive ring when an external force acts, reducing the risk of damage. A plurality of notches (19) are provided at an inner rim of the drive ring (14), and, among inner circumferential surfaces (14a, 14b, 14c, 14d, 14e, 14f, 14g, and 14h) located between the notches (19), when a driving force for rotating the drive ring (14) is applied, the inner diameters of the inner circumferential surfaces (14e, 14f, 14g, and 14h) where the contact load with the outer circumferential surface of a mount becomes large are made larger than the outer diameter of the outer circumferential surface.

摘要翻译： 当通过旋转驱动环来改变喷嘴叶片角度时，可以减小在驱动环的内周表面和安装件的外圆周表面之间产生的接触负载，从而允许驱动环平稳地旋转并减少磨损量 和驱动力。 当外力作用时，还可以减小在驱动环处产生的冲击力，例如发动机振动，减少损坏的风险。 在驱动环（14）的内缘设有多个切口（19），在位于切口（14）的内周面（14a，14b，14c，14d，14e，14f，14g，14h） 如图19所示，当施加用于使驱动环（14）旋转的驱动力时，与底座的外周面的接触负荷变大的内周面（14e，14f，14g，14h）的内径变大 被制成大于外周面的外径。

公开(公告)号：US07281155B1

公开(公告)日：2007-10-09

申请号：US09359767

申请日：1999-07-22

申请人： Satoshi Eto ,  Masato Matsumiya ,  Toshimi Ikeda ,  Yuki Ishii ,  Akira Kikutake ,  Kuninori Kawabata

发明人： Satoshi Eto ,  Masato Matsumiya ,  Toshimi Ikeda ,  Yuki Ishii ,  Akira Kikutake ,  Kuninori Kawabata

IPC分类号： H02H3/05

CPC分类号： G11C29/78

摘要： A semiconductor memory device having a shift redundancy function includes a switch circuit for changeably connecting a plurality of decode signal lines decoding an address signal to a plurality of selecting lines and redundancy selecting lines, and executes a switch operation for shifting at least one of a plurality of decode lines in the direction of a first redundancy selecting line positioned at one of the ends among a plurality of selecting lines or a second switch operation for shifting at least one of the decode lines in the direction of a second redundancy selecting line positioned at the other end among the selecting lines or both of the first and second operations when any fault occurs in a plurality of selecting lines. The semiconductor memory device preferably includes two or more first redundancy selecting lines positioned at one of the ends of a plurality of selecting lines, two or more second redundancy selecting lines positioned at the other end, and first and second switch units disposed in two stages. When any fault selecting line occurs, the first switch unit executes a first switch operation for shifting at least one of the decode signal lines in the direction of the first redundancy selecting line or a second switch operation for shifting the same in the direction of the second redundancy selecting line, or the second switch unit executes a third switch operation for shifting at least one decode signal line in the direction of the first redundancy selecting line or a fourth switch operation for shifting it in the direction of the second redundancy selecting line.

摘要翻译： 具有移位冗余功能的半导体存储器件包括用于将解码地址信号的多条解码信号线与多条选择线和冗余选择线可变地连接的开关电路，并且执行用于移位多个选择线和冗余选择线中的至少一个的切换操作 在位于多个选择线中的一端的第一冗余选择线的方向上的解码线的第二切换操作或用于沿着位于所述多个选择线的第二冗余选择线的方向移位至少一条解码线的第二切换操作 在多个选择线中发生任何故障时，选择线中的另一端或第一和第二操作两者。 半导体存储器件优选地包括位于多个选择线的一端的两个或更多个第一冗余选择线，以及位于另一端的两个或更多个第二冗余选择线以及分两个阶段布置的第一和第二开关单元。 当发生任何故障选择线时，第一开关单元执行第一开关操作，用于沿第一冗余选择线的方向移位至少一个解码信号线，或者执行第二开关操作，以使其在第二冗余选择线的方向上移位 冗余选择线或者第二开关单元执行用于在第一冗余选择线的方向上移位至少一个解码信号线的第三开关操作或者用于在第二冗余选择线的方向上移位的第四开关操作。

公开(公告)号：US07079443B2

公开(公告)日：2006-07-18

申请号：US10631752

申请日：2003-08-01

申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC分类号： G11C8/08

CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

公开(公告)号：US06201378B1

公开(公告)日：2001-03-13

申请号：US09301203

申请日：1999-04-28

申请人： Satoshi Eto ,  Masato Matsumiya ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

发明人： Satoshi Eto ,  Masato Matsumiya ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

IPC分类号： G05F316

CPC分类号： G11C11/4074 ,  G11C5/147 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4099

摘要： A semiconductor integrated circuit producing a given output voltage includes first and second operational amplifiers, and first and second transistors. The first and second operational amplifiers detect a voltage difference between a voltage applied to an input terminal and at least one reference voltage. The first and second transistors are turned ON or turned OFF according to the levels of voltages output from the first and second operational amplifiers. The first operational amplifier receives the output voltage at the input terminal. When the level of the output voltage becomes lower than the reference voltage, the first operational amplifier allows the first transistor to operate so as to raise the output voltage. In contrast, the second operational amplifier receives the output voltage at the input terminal. When the level of the output voltage exceeds the reference voltage, the second operational amplifier allows the second transistor to operate so as to lower the output voltage.

摘要翻译： 产生给定输出电压的半导体集成电路包括第一和第二运算放大器以及第一和第二晶体管。 第一和第二运算放大器检测施加到输入端的电压与至少一个参考电压之间的电压差。 根据从第一和第二运算放大器输出的电压的电平，第一和第二晶体管导通或截止。 第一个运算放大器在输入端接收输出电压。 当输出电压的电平变得低于参考电压时，第一运算放大器允许第一晶体管工作，以便提高输出电压。 相反，第二运算放大器在输入端接收输出电压。 当输出电压的电平超过参考电压时，第二运算放大器允许第二晶体管工作，以降低输出电压。

公开(公告)号：US08348601B2

公开(公告)日：2013-01-08

申请号：US12671163

申请日：2008-10-02

申请人： Noriyuki Hayashi ,  Yasuaki Jinnai ,  Hiroshi Suzuki ,  Yuki Ishii

发明人： Noriyuki Hayashi ,  Yasuaki Jinnai ,  Hiroshi Suzuki ,  Yuki Ishii

IPC分类号： F01D17/16

CPC分类号： F01D17/165 ,  F05D2220/40 ,  F05D2250/182 ,  F05D2250/19 ,  F05D2260/30 ,  F05D2260/56

摘要： When changing a nozzle blade angle by rotating a drive ring, a contact load generated between an inner circumferential surface of the drive ring and an outer circumferential surface of a mount can be reduced, allowing the drive ring to rotate smoothly and reducing the amount of wear and a driving force. It is also possible to reduce an impact force, such as engine vibrations, generated at the drive ring when an external force acts, reducing the risk of damage. A plurality of notches (19) are provided at an inner rim of the drive ring (14), and, among inner circumferential surfaces (14a, 14b, 14c, 14d, 14e, 14f, 14g, and 14h) located between the notches (19), when a driving force for rotating the drive ring (14) is applied, the inner diameters of the inner circumferential surfaces (14e, 14f, 14g, and 14h) where the contact load with the outer circumferential surface of a mount becomes large are made larger than the outer diameter of the outer circumferential surface.

摘要翻译： 当通过旋转驱动环来改变喷嘴叶片角度时，可以减小在驱动环的内周表面和安装件的外圆周表面之间产生的接触负载，从而允许驱动环平稳地旋转并减少磨损量 和驱动力。 当外力作用时，还可以减小在驱动环处产生的冲击力，例如发动机振动，减少损坏的风险。 在驱动环（14）的内缘设有多个切口（19），在位于切口（14）的内周面（14a，14b，14c，14d，14e，14f，14g，14h） 如图19所示，当施加用于使驱动环（14）旋转的驱动力时，与底座的外周面的接触负荷变大的内周面（14e，14f，14g，14h）的内径变大 被制成大于外周面的外径。

公开(公告)号：US20060098523A1

公开(公告)日：2006-05-11

申请号：US11313963

申请日：2005-12-22

申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC分类号： G11C8/00

CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

公开(公告)号：US06198683B1

公开(公告)日：2001-03-06

申请号：US09563846

申请日：2000-05-04

申请人： Yuki Ishii ,  Shinichi Yamada

发明人： Yuki Ishii ,  Shinichi Yamada

IPC分类号： G11C700

CPC分类号： G11C5/147

摘要： A memory device comprising: a step-down voltage generating circuit for generating a first step-down voltage by stepping down a power-supply voltage, and a second step-down voltage lower than said first step-down voltage; a peripheral circuit to which said first step-down voltage is supplied; and a memory core to which said second step-down voltage is supplied, wherein said step-down voltage generating circuit comprises a first step-down circuit for generating said first step-down voltage from said power-supply voltage supplied thereto, and a second step-down circuit for generating said second step-down voltage from said first step-down voltage supplied thereto, and a consumed current corresponding to said second step-down voltage is a first current value in a first operating period, and a second current value lower than said first current value in a second operating period.

摘要翻译： 一种存储装置，包括：降压电压产生电路，用于通过降低电源电压和低于所述第一降压电压的第二降压电压产生第一降压电压; 提供所述第一降压电压的外围电路; 以及提供所述第二降压电压的存储器芯，其中所述降压电压产生电路包括用于从所提供的所述电源电压产生所述第一降压电压的第一降压电路，以及第二降压电路 降压电路，用于从提供给其的所述第一降压电压产生所述第二降压电压，并且与所述第二降压电压相对应的消耗电流是第一操作周期中的第一电流值，以及第二电流值 在第二操作期间低于所述第一电流值。