公开(公告)号：US06703902B2

公开(公告)日：2004-03-09

申请号：US10253072

申请日：2002-09-24

申请人： Phil-Jae Jeon ,  Myoung-su Lee

发明人： Phil-Jae Jeon ,  Myoung-su Lee

IPC分类号： H03L708

CPC分类号： H03C3/0975 ,  H03C3/0958 ,  H03L7/0996 ,  H03L7/0998 ,  H03L7/18

摘要： A phase locked loop (PLL) for reducing electromagnetic interference (EMI) is provided. The PLL is not sensitive to a manufacturing process, consumes less power, occupies a small layout space, and can flexibly control a modulation frequency and a modulation rate flexibly. The PLL for reducing the EMI controls the signals having a phase difference, which is n-times (where n is an integer) the basic delay time of the output signals from a voltage controlled oscillator (VCO), and determines the modulation rate. Then, the PLL repeats the procedure during the cycle of a pre-defined modulation frequency. The PLL for reducing the EMI not only reduces the EMI, but also does not require a ROM. Therefore, the layout space can be reduced and broad frequency ranges can be obtained. In addition, since the phase difference of the output signals of the VCO is controlled by logic circuits, the PLL is insensitive to changes in the manufacturing process.

摘要翻译： 提供了用于降低电磁干扰（EMI）的锁相环（PLL）。 PLL对制造过程不敏感，功耗较小，布局空间小，灵活控制调制频率和调制速率。 用于降低EMI的PLL控制具有来自压控振荡器（VCO）的输出信号的基本延迟时间的n倍（其中n是整数）的相位差的信号，并且确定调制率。 然后，PLL在预定义的调制频率的周期中重复该过程。 用于降低EMI的PLL不仅降低了EMI，而且不需要ROM。 因此，可以减小布局空间并且可以获得宽的频率范围。 此外，由于VCO的输出信号的相位差由逻辑电路控制，所以PLL对制造过程的变化不敏感。

公开(公告)号：US06504442B2

公开(公告)日：2003-01-07

申请号：US09826598

申请日：2001-04-05

申请人： Richard Jordan ,  Anthony J. Perri

发明人： Richard Jordan ,  Anthony J. Perri

IPC分类号： H03L708

CPC分类号： H03L7/00 ,  H03L3/00

摘要： A digitally controlled oscillator includes an adjustable signal generating circuit adapted to generate an oscillation signal. A feedback loop receives the oscillation signal from the adjustable signal generating circuit. The feedback loop detects error in the oscillation signal and produces an error signal based on the error. The control logic circuit receives the error signal from the feedback loop and maintains the oscillation signal within a predetermined error range. Also, a state device that is connected to the adjustable signal generating circuit maintains a previous operating state of the adjustable signal generating circuit when the digitally controlled oscillator is temporarily powered down. When the digitally controlled oscillator is powered up after being temporarily powered down, the control logic starts the adjustable signal generating circuit at the previous operating state based upon data maintained within the state device, and restarts the feedback loop and error processing circuits in a way to avoid oscillator adjustments based on old data.

公开(公告)号：US06337589B1

公开(公告)日：2002-01-08

申请号：US09130606

申请日：1998-08-07

申请人： Tsukasa Ooishi

发明人： Tsukasa Ooishi

IPC分类号： H03L708

CPC分类号： G11C7/222 ,  G11C7/22 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/113

摘要： A PLL is provided with separate phase and frequency adjustment circuits to adjust the frequency of a produced internal clock independently from adjusting its phase. The phase adjustment circuit determines a phase error between the internal clock and an external clock, and averages the phase error over a predetermined time period to produce the corresponding control current. The frequency adjustment circuit detects the difference between the frequency of the internal clock and the frequency of the external clock to determine a frequency error. An accumulator accumulates the frequency error during the predetermined time period to produce the corresponding control current. Based on values of the control currents produced by the phase and frequency adjustment circuits, a current calculator calculates a resulting value of the control current to be applied to a CCO to modify its frequency so as reduce the frequency and phase differences.

摘要翻译： PLL提供有单独的相位和频率调节电路，以独立调整其相位来调节所产生的内部时钟的频率。 相位调整电路确定内部时钟与外部时钟之间的相位误差，并且在预定时间段内平均相位误差以产生相应的控制电流。 频率调整电路检测内部时钟的频率与外部时钟的频率之间的差异，以确定频率误差。 累加器在预定时间段内累积频率误差，产生相应的控制电流。 基于由相位和频率调整电路产生的控制电流的值，电流计算器计算要施加到CCO的控制电流的结果值以修改其频率，从而降低频率和相位差。

公开(公告)号：US06313709B1

公开(公告)日：2001-11-06

申请号：US09647235

申请日：2000-09-25

申请人： Eizo Nishimura ,  Masamichi Nakajima

发明人： Eizo Nishimura ,  Masamichi Nakajima

IPC分类号： H03L708

CPC分类号： H03L7/191 ,  H03L7/14

摘要： The present invention is concerned with a PLL comprising the phase comparator 20, loop filter 21, VCO 14 and loop counter 22, wherein there are further provided a prediction window circuit 23 for outputting HWIN (prediction window signal) for predicting the point at which the REF (reference signal) is generated, an omission compensation circuit 24 for detecting the omission of the REF at the time when HWIN is outputted and outputting d.VARX (the second correction signal) to offset the phase difference between d.REFX (the first correction signal) and the VAR (comparison signal) so that the phase comparator 20 outputs the signals Ph1 and Ph2 corresponding to the phase difference between the VAR and the d.REFX and the signals Ph1 and Ph2 corresponding to the phase difference between d.REFC and d.VARX when the omission of the REF has occurred, thereby enabling proper compensation for omission to be made and stable CLK (clock) to be generated even when VCO 14 having a very wide frequency variation range is used. Further, a circuit for generating the gate control signal Gc by advancing the phase of the VAR by 1 clock so that not only the 3-state signal corresponding to the phase difference between the REF and VAR can be outputted but also the 3-state buffers, which can be controlled in active state according to the signal Gc can be made available, whereby accurate control voltage corresponding to the phase difference can be outputted to the VCO to generate stable CLK even when the phase difference between the REF and VAR is close to 0.

摘要翻译： 本发明涉及包括相位比较器20，环路滤波器21，VCO14和环路计数器22的PLL，其中还提供了预测窗口电路23，用于输出预测窗口信号的预测窗口电路23， 产生REF（参考信号），省略补偿电路24，用于检测在输出HWIN时省略REF，并输出d.VARX（第二校正信号）以偏移d.REFX（第一 校正信号）和VAR（比较信号），使得相位比较器20输出对应于VAR和d.REFX之间的相位差的信号Ph1和Ph2以及对应于d.REFC之间的相位差的信号Ph1和Ph2 并且当省略REF时，d.VARX发生，从而即使在具有非常宽的频率va的VCO14时也能够产生适当的省略补偿以及稳定的CLK（时钟） 使用对照范围。 另外，通过将VAR的相位推进1个时钟来产生栅极控制信号Gc的电路，使得不仅可以输出与REF和VAR之间的相位差相对应的3态信号，而且还可以输出3态缓冲器 可以根据信号Gc被控制在有效状态，由此可以将对应于相位差的精确控制电压输出到VCO以产生稳定的CLK，即使当REF和VAR之间的相位差接近于 0。

公开(公告)号：US06278331B1

公开(公告)日：2001-08-21

申请号：US09282081

申请日：1999-03-30

申请人： James M. Piccione

发明人： James M. Piccione

IPC分类号： H03L708

CPC分类号： G06F1/08 ,  H03K5/135 ,  H03L1/00

摘要： The present invention relates to a system and method for compensating IC parameters. According to an embodiment of the present invention, a die of an IC wafer is coupled with a compensation circuit that classifies the die into various types. Examples of types include fast, typical, and slow. The assigned type may be used in a special oscillator that compensates for variations from a die to a predetermined criteria. According to an embodiment of the present invention, a slow die directs a signal that moves through a relatively short path, a fast die directs a signal that moves through a relatively long path, and a typical die directs a signal that moves through a relatively medium length path in the compensation circuit. Accordingly, each die on a wafer may be coupled with a compensation circuit such that the compensation circuit selects a path of a circuit that adjusts the frequency produced by the dies to produce a batch of ICs that would meet the predetermined criteria for the vast majority of the dies. A large number of useable Ics would be produced by adjusting the frequency produced by the ICs which would conventionally not meet the predetermined criteria to a frequency that does meet the predetermined criteria.

摘要翻译： 本发明涉及用于补偿IC参数的系统和方法。 根据本发明的实施例，IC晶片的管芯与将所述管芯分类成各种类型的补偿电路耦合。 类型的例子包括快速，典型和慢。 分配的类型可以用于补偿从模具到预定标准的变化的特殊振荡器。 根据本发明的一个实施例，一个缓冲管芯引导移动通过相对较短路径的信号，一个快速管芯引导一条通过相对长的路径移动的信号，一个典型的管芯引导一个通过相对介质移动的信号 补偿电路中的长度路径。 因此，晶片上的每个管芯可以与补偿电路耦合，使得补偿电路选择调整由管芯产生的频率的电路的路径以产生满足绝大多数的预定标准的一批IC 死亡。 通过将通常不符合预定标准的IC产生的频率调整到满足预定标准的频率，将产生大量可用的Ic。

公开(公告)号：US06259328B1

公开(公告)日：2001-07-10

申请号：US09466352

申请日：1999-12-17

申请人： Jan Wesolowski

发明人： Jan Wesolowski

IPC分类号： H03L708

CPC分类号： H03L7/146 ,  H03L7/107 ,  H03L7/143 ,  H03L7/197 ,  H04J3/0688 ,  H04L7/0331

摘要： Methods and systems are disclosed for eliminating a phase transient of a controlled frequency oscillator caused by replacing a first reference signal by a second reference signal when the first reference signal becomes corrupted or otherwise unavailable, and for running a controlled frequency oscillator in a frequency-controlled holdover mode. The contradictory requirements of using a relatively low-cost controlled frequency oscillator tunable over a relatively wide frequency range and achieving high stability of its frequency in holdover mode are satisfied.

摘要翻译： 公开了一种用于消除受控频率振荡器的相位瞬变的方法和系统，该控制频率振荡器在第一参考信号变得损坏或不可用时将第一参考信号替换为第二参考信号，并且用于在受控频率振荡器 保持模式。 满足在相对宽的频率范围内可调谐的相对低成本的受控频率振荡器并且在保持模式下实现其频率的高稳定性的矛盾要求。

公开(公告)号：US06252465B1

公开(公告)日：2001-06-26

申请号：US09427582

申请日：1999-10-27

申请人： Hisao Katoh

发明人： Hisao Katoh

IPC分类号： H03L708

CPC分类号： H03L7/0891 ,  H03L7/081 ,  H03L7/0995

摘要： A phase comparator circuit reducing the effects of offset and jitter, and a data Phase Locked Loop circuit incorporating the phase comparator circuit. The phase comparator circuit includes a Delay Locked Loop circuit for outputting a delay, signal PLDTD with a delay according to an oscillation frequency of a voltage controlled oscillator, with respect to an input data PLDT, a D-type flip-flop for outputting a delay signal PLDTL by latching an input data PLCK according to an oscillation clock PLCK output from a voltage controlled oscillator, and a phase comparator for comparing phases of delay signals PLDTD and PLDTL.

摘要翻译： 相位比较器电路减少偏移和抖动的影响，以及包含相位比较器电路的数据锁相环电路。 相位比较器电路包括用于根据输入数据PLDT输出延迟的延迟锁定电路，具有根据压控振荡器的振荡频率的延迟的信号PLDTD，用于输出延迟的D型触发器 信号PLDTL，通过根据从压控振荡器输出的振荡时钟PLCK锁存输入数据PLCK，以及相位比较器，用于比较延迟信号PLDTD和PLDTL的相位。

公开(公告)号：US06229399B1

公开(公告)日：2001-05-08

申请号：US09060145

申请日：1998-04-15

申请人： Daisuke Tobise ,  Hisashi Adachi ,  Hidenobu Kato

发明人： Daisuke Tobise ,  Hisashi Adachi ,  Hidenobu Kato

IPC分类号： H03L708

CPC分类号： H03L7/1976 ,  H03L7/093 ,  H03L7/099 ,  H03L7/18 ,  H03L2207/06

摘要： A multiband PLL frequency synthesizer is disclosed which includes: a reference signal generation circuit for generating a reference signal of which frequency is controlled; a phase comparator for generating a phase difference signal; a low-pass filter circuit for low-pass-filtering the phase difference signal with one of a plurality of cutoff frequencies selected; a VCO for generating and outputting a LO signal according to an output of the low-pass filter; a frequency dividing circuit having an integer frequency dividing mode and a fraction frequency dividing mode to supply the frequency-divided signal to the phase comparator; and a control circuit for supplying the reference frequency control signal to the reference signal generation circuit, a filter control signal to the low-pass filter circuit, and frequency dividing control signal (data) to the frequency dividing circuit in accordance with a frequency command signal. The cutoff frequencies and the frequency dividing mode are selected to control the loop condition in accordance with the frequency command signal.

摘要翻译： 公开了一种多频带PLL频率合成器，其包括：用于产生控制频率的参考信号的参考信号产生电路; 用于产生相位差信号的相位比较器; 低通滤波器电路，用于对选择的多个截止频率之一进行低通滤波所述相位差信号; 用于根据低通滤波器的输出产生和输出LO信号的VCO; 具有整数分频模式和分频分频模式的分频电路，用于将分频信号提供给相位比较器; 以及用于将参考频率控制信号提供给参考信号产生电路的控制电路，到低通滤波器电路的滤波器控制信号和根据频率指令信号的分频电路的分频控制信号（数据） 。 选择截止频率和分频模式以根据频率指令信号来控制环路状况。

公开(公告)号：US06229363B1

公开(公告)日：2001-05-08

申请号：US09224354

申请日：1999-01-04

申请人： Satoshi Eto ,  Masato Matsumiya ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

发明人： Satoshi Eto ,  Masato Matsumiya ,  Masato Takita ,  Toshikazu Nakamura ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Masatomo Hasegawa ,  Toru Koga ,  Yuki Ishii

IPC分类号： H03L708

CPC分类号： G11C7/1057 ,  G06F1/10 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： A semiconductor device having the function of generating an internal clock signal delayed by a predetermined phase by adjusting the phase of an external clock signal, includes a first clock phase circuit for roughly adjusting the phase of the external clock signal; and a second clock phase adjusting circuit for controlling the phase of the internal clock signal with higher accuracy than the first clock phase adjusting circuit. The semiconductor device having such a construction executes phase comparisons by the first and second clock phase adjusting circuits independently of each other, and when a phase control operation by the second clock phase adjusting circuit is made subordinate to that of the first clock phase adjusting circuit, the delay time of each of a plurality of delay elements inside the first clock phase adjusting circuit is set to a value larger than a power source jitter resulting from a noise of a power source and a jitter of the external clock signal.

摘要翻译： 具有通过调整外部时钟信号的相位而产生延迟预定相位的内部时钟信号的功能的半导体器件包括用于大致调整外部时钟信号的相位的第一时钟相位电路; 以及第二时钟相位调整电路，用于以比第一时钟相位调整电路更高的精度来控制内部时钟信号的相位。 具有这种结构的半导体器件执行第一和第二时钟相位调整电路彼此独立的相位比较，并且当第二时钟相位调整电路的相位控制操作从属于第一时钟相位调整电路的相位控制操作时， 第一时钟相位调整电路内的多个延迟元件中的每一个的延迟时间被设定为大于由电源的噪声和外部时钟信号的抖动导致的电源抖动的值。

公开(公告)号：US06664830B2

公开(公告)日：2003-12-16

申请号：US09997721

申请日：2001-11-30

申请人： James E. Miller

发明人： James E. Miller

IPC分类号： H03L708

CPC分类号： H03L7/089 ,  H03L7/0814 ,  H03L7/093

摘要： Circuits and methods are provided that reduce, if not prevent, the adverse effects of transient noise on phase adjustments made by digital delay lock loop (DLL) circuits, which typically generate a periodic output signal having a particular phase relationship with a periodic input signal. A digital low pass filter of a DLL circuit includes circuitry, such as, for example, a thermometer register, coupled to receive the outputs of a DLL phase detector. The low pass filter prevents the DLL circuit from making frequent changes to the phase of the DLL output signal.