公开(公告)号：US20080144417A1

公开(公告)日：2008-06-19

申请号：US11998428

申请日：2007-11-30

申请人： Yasuyuki Eguchi ,  Shinya Fujioka ,  Yoshiaki Okuyama

发明人： Yasuyuki Eguchi ,  Shinya Fujioka ,  Yoshiaki Okuyama

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/406 ,  G11C8/12 ,  G11C11/40622

摘要： A refresh register stores disable block information indicating a memory block whose refresh operation is to be disabled. A refresh control circuit periodically executes the refresh operation of a memory block except the memory block corresponding to the disable block information. During an access cycle to one of the memory blocks, the register control circuit writes the disable block information to the refresh register according to an external input. Consequently, in order to rewrite the refresh register, it is not necessary to use an additional operation cycle to the access cycle. Since there is no need to insert an extra operation cycle, it is possible to change a memory area to be refreshed without lowering effective efficiency of access cycles. As a result, power consumption can be reduced.

摘要翻译： 刷新寄存器存储指示将被禁用刷新操作的存储器块的禁止块信息。 刷新控制电路周期性地执行除了与禁用块信息相对应的存储块之外的存储器块的刷新操作。 在对存储器块之一的访问周期期间，寄存器控制电路根据外部输入将该禁止块信息写入刷新寄存器。 因此，为了重写刷新寄存器，不需要对访问周期使用附加的操作周期。 由于不需要插入额外的操作周期，因此可以改变要刷新的存储区域，而不会降低访问周期的有效效率。 结果，可以降低功耗。

公开(公告)号：US20060291307A1

公开(公告)日：2006-12-28

申请号：US11260486

申请日：2005-10-28

申请人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

发明人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

IPC分类号： G11C29/00

CPC分类号： G11C29/06 ,  G11C29/10 ,  G11C2029/0405 ,  G11C2029/1204 ,  G11C2029/3602

摘要： A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.

摘要翻译： 包括在每个步骤中施加相同时间长度的电压的第一至第六步骤的老化测试被施加到具有交替排列的位线对的半导体存储器，其中位线彼此交叉并且位线 对，其中位线彼此平行的非扭转结构。 由于可以对所有位线施加应力的时间长度，所以在位线之间施加应力的时间长度不会发生偏差。 可以防止记忆单元的特性从老化测试过度恶化。 此外，在第一至第六步骤中可以使不具有应力的位线的数量最小化。 因此，可以增加施加了应力的位线的比例，这降低了老化测试时间。 因此，可以降低测试成本。

公开(公告)号：US06847570B2

公开(公告)日：2005-01-25

申请号：US10300800

申请日：2002-11-21

申请人： Shinya Fujioka ,  Yoshiaki Okuyama

发明人： Shinya Fujioka ,  Yoshiaki Okuyama

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1063 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076

摘要： A refresh control circuit generates a refresh request in a predetermined cycle. A first burst control circuit outputs a predetermined number of strobe signals in accordance with an access command. A burst access operation is executed by an access command. A data input/output circuit successively inputs data to be transferred to a memory cell array or successively outputs data supplied from the memory cell array, in synchronization with the strobe signals. An arbiter determines which of a refresh operation or a burst access operation is to be executed first, when the refresh request and the access command conflict with each other. Therefore, the refresh operation and burst access operation can be sequentially executed without being overlapped. As a result, read data can be outputted at a high speed, and write data can be inputted at a high speed. That is, the data transfer rate can be improved.

摘要翻译： 刷新控制电路以预定的周期生成刷新请求。 第一突发控制电路根据访问命令输出预定数量的选通信号。 通过访问命令执行突发存取操作。 数据输入/输出电路连续输入要传送到存储单元阵列的数据，或者与选通信号同步地连续输出从存储单元阵列提供的数据。 当刷新请求和访问命令彼此冲突时，仲裁器确定首先执行刷新操作或突发存取操作中的哪一个。 因此，可以顺序地执行刷新操作和突发存取操作而不重叠。 结果，可以高速地输出读取数据，并且可以高速地输入写入数据。 也就是说，可以提高数据传输速率。

公开(公告)号：US06621750B2

公开(公告)日：2003-09-16

申请号：US10155029

申请日：2002-05-28

申请人： Yoshiaki Okuyama ,  Shinya Fujioka ,  Kota Hara ,  Katsuhiro Mori

发明人： Yoshiaki Okuyama ,  Shinya Fujioka ,  Kota Hara ,  Katsuhiro Mori

IPC分类号： G11C700

CPC分类号： G11C29/808 ,  G11C29/812 ,  G11C29/848

摘要： A redundancy memory circuit stores a defect address indicating a defective memory cell row. A redundancy control circuit disables the defective memory cell row corresponding to the defect address stored in the redundancy memory circuit and enables a redundancy memory cell row in the memory block containing the defective memory cell row. Moreover, in the other memory blocks, the redundancy control circuit disables memory cell rows corresponding to the defective memory cell row and enables redundancy memory cell rows instead of these memory cell rows. Consequently, not only the memory block having the defective memory cell row but one of the memory cell rows in the other memory blocks is always also relieved. Thus, the redundancy memory circuit can be shared among all the memory blocks with a reduction in the number of redundancy memory circuits. As a result, the semiconductor memory can be reduced in chip size.

公开(公告)号：US07730232B2

公开(公告)日：2010-06-01

申请号：US11113181

申请日：2005-04-25

申请人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

发明人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

IPC分类号： G06F13/00

CPC分类号： G06F12/0804 ,  G06F2212/2022 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C16/06 ,  G11C16/3454

摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.

摘要翻译： 提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。 传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从 响应于确认完成数据传送的传送状态。

公开(公告)号：US20080285370A1

公开(公告)日：2008-11-20

申请号：US11902841

申请日：2007-09-26

申请人： Yoshiaki Okuyama

发明人： Yoshiaki Okuyama

IPC分类号： G11C11/406

CPC分类号： G11C11/406 ,  G11C11/40622

摘要： An access control unit performs an access operation and a refresh operation of a memory block in response to an access request and a refresh request. The access control unit operates respective memory blocks in a single-cell mode or a twin-cell mode according to cell mode information in a mode setting unit. A refresh control unit disables the refresh operation of the memory block the nonperformance of which is set in the mode setting unit. By operating only the memory block requiring high reliability in the twin-cell mode and selectively disabling the refresh operation of the memory block, a semiconductor memory can be operated optimally according to a specification of a system, enabling a reduction in power consumption.

摘要翻译： 访问控制单元响应于访问请求和刷新请求执行存储块的访问操作和刷新操作。 访问控制单元根据模式设置单元中的小区模式信息以单小区模式或双小区模式操作各个存储块。 刷新控制单元禁止在模式设置单元中设置其不执行的存储器块的刷新操作。 通过仅操作在双电池模式下需要高可靠性的存储器块并且选择性地禁用存储器块的刷新操作，可以根据系统的规格最佳地操作半导体存储器，从而能够降低功耗。

公开(公告)号：US07362630B2

公开(公告)日：2008-04-22

申请号：US11714766

申请日：2007-03-07

申请人： Kaoru Mori ,  Yoshiaki Okuyama

发明人： Kaoru Mori ,  Yoshiaki Okuyama

IPC分类号： G11C29/00

CPC分类号： G11C29/808 ,  G11C29/838

摘要： In order to give all memory blocks the same structure, a redundancy word line and a redundancy bit line are formed in each memory block. A redundancy column selection line is wired in common to the memory blocks. Column redundancy circuits are formed to correspond to respective memory groups each of which consists of a prescribed number of memory blocks, and become effective according to enable signals. A column redundancy selection circuit activates an enable signal according to a block address signal when all row hit signals are deactivated. When one of the row hit signals is activated, the column redundancy selection circuit activates the enable signal corresponding to the activated row hit signal. Since the column redundancy circuit for an arbitrary memory group can be made effective according to the row hit signals, failure relief efficiency can be increased without deteriorating the electric characteristic during an access operation.

摘要翻译： 为了给予所有存储块相同的结构，在每个存储块中形成冗余字线和冗余位线。 冗余列选择线公共地连接到存储器块。 列冗余电路形成为对应于各自的存储器组，每个存储器组由规定数量的存储块组成，并且根据使能信号变为有效。 当所有行命中信号被去激活时，列冗余选择电路根据块地址信号激活使能信号。 当行命中信号之一被激活时，列冗余选择电路激活对应于激活的行命中信号的使能信号。 由于可以根据行命中信号使任意存储器组的列冗余电路有效，可以在不使访问操作期间的电特性恶化的情况下增加故障排除效率。

公开(公告)号：US07200059B2

公开(公告)日：2007-04-03

申请号：US11260486

申请日：2005-10-28

申请人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

发明人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

IPC分类号： G11C29/00

CPC分类号： G11C29/06 ,  G11C29/10 ,  G11C2029/0405 ,  G11C2029/1204 ,  G11C2029/3602

摘要： A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.

摘要翻译： 包括在每个步骤中施加相同时间长度的电压的第一至第六步骤的老化测试被施加到具有交替排列的位线对的半导体存储器，其中位线彼此交叉并且位线 对，其中位线彼此平行的非扭转结构。 由于可以对所有位线施加应力的时间长度，所以在位线之间施加应力的时间长度不会发生偏差。 可以防止记忆单元的特性从老化测试过度恶化。 此外，在第一至第六步骤中可以使不具有应力的位线的数量最小化。 因此，可以增加施加了应力的位线的比例，这降低了老化测试时间。 因此，可以降低测试成本。

公开(公告)号：US20060280015A1

公开(公告)日：2006-12-14

申请号：US11260201

申请日：2005-10-28

申请人： Yoshiaki Okuyama

发明人： Yoshiaki Okuyama

IPC分类号： G11C7/00

CPC分类号： G11C11/40603 ,  G11C11/406 ,  G11C11/40626 ,  G11C2211/4061 ,  G11C2211/4067

摘要： An oscillator generates a refresh request signal periodically. A storing circuit changes a stored value by a predetermined value in response to the refresh request signal and returns the stored value by one in response to a refresh operation. A store control circuit, when a state detecting circuit detects a change of an operational state of a semiconductor memory, increases or decreases the predetermined value which the storing circuit uses. A refresh decision circuit outputs refresh signals of a number corresponding to the stored value until the stored value returns to an initial value. This makes it possible to change the frequency of the refresh operations according to a change of the operational state without changing an oscillation cycle of the oscillator. Without unnecessary oscillation of the oscillator, it is possible to decrease a standby current of the semiconductor memory.

摘要翻译： 振荡器周期性地产生刷新请求信号。 存储电路响应于刷新请求信号而改变存储值预定值，并响应于刷新操作将存储值返回一个。 存储控制电路当状态检测电路检测出半导体存储器的工作状态的变化时，增加或减少存储电路使用的预定值。 刷新判定电路输出对应于存储值的数字的刷新信号，直到存储的值返回到初始值。 这使得可以在不改变振荡器的振荡周期的情况下根据操作状态的变化来改变刷新操作的频率。 没有振荡器的不必要的振荡，可以减少半导体存储器的待机电流。

公开(公告)号：US07321517B2

公开(公告)日：2008-01-22

申请号：US11260200

申请日：2005-10-28

申请人： Hitoshi Ikeda ,  Kaoru Mori ,  Yoshiaki Okuyama

发明人： Hitoshi Ikeda ,  Kaoru Mori ,  Yoshiaki Okuyama

IPC分类号： G11C7/00

CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C29/025

摘要： An equalizing circuit connects a pair of bit lines to each other in response to the activation of an equalizing control signal and connects the pair of bit lines to a precharge voltage line. An equalizing control circuit deactivates the equalizing control signal in response to the activation of a first timing signal. A word line driving circuit activates one of word lines in response to the activation of a second timing signal. A first signal generating circuit of a timing control circuit generates the first timing signal. A second signal generating circuit of the timing control circuit activates the second timing signal after the deactivation of the equalizing control signal accompanying the activation of the first timing signal. A delay control circuit of the second signal generating circuit delays an activation timing of the second timing signal in a test mode from that in a normal mode.

摘要翻译： 均衡电路响应于均衡控制信号的激活而将一对位线彼此连接，并将一对位线连接到预充电电压线。 均衡控制电路响应于第一定时信号的激活而去激活均衡控制信号。 字线驱动电路响应于第二定时信号的激活而激活字线之一。 定时控制电路的第一信号发生电路产生第一定时信号。 定时控制电路的第二信号发生电路在伴随第一定时信号的激活的均衡控制信号的去激活之后激活第二定时信号。 第二信号发生电路的延迟控制电路将测试模式中的第二定时信号的激活定时与正常模式中的激活定时相比较。